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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Compact, reliable thermostat provides a temperature readout signal and a continuous temperature-control output for temperature monitoring by automatic checkout equipment or telemetry systems. It employs a solid state circuit in a housing rigidly attached to a thermistor probe.
The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.
Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.
This paper describes the design of a digital control system for control of magnetic bearings used in a spaceborne cryogenic cooler. The cooler was developed by Philips Laboratories for the NASA Goddard Space Flight Center. Six magnetic bearing assemblies are used to levitate the piston, displacer, and counter-balance of the cooler. The piston and displacer are driven by linear motors in accordance with Stirling cycle thermodynamic principles to produce the desired cooling effect. The counter-balance is driven by a third linear motor to cancel motion induced forces that would otherwise be transmitted to the spacecraft. An analog control system is currently used for bearing control. The purpose of this project is to investigate the possibilities for improved performance using digital control. Areas for potential improvement include transient and steady state control characteristics, robustness, reliability, adaptability, alternate control modes, size, weight, and cost. The present control system is targeted for the Intel 80196 microcontroller family. The eventual introduction of application specific integrated circuit (ASIC) technology to this problem may produce a unique and elegant solution both here and in related industrial problems.
The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.
Semiconductor chips based on MEMS (Micro-Electro-Mechanical Systems) technology, such as sensors, transducers, and actuators, are becoming widely used in today s electronics due to their high performance, low power consumption, tolerance to shock and vibration, and immunity to electro-static discharge. In addition, the MEMS fabrication process allows for the miniaturization of individual chips as well as the integration of various electronic circuits into one module, such as system-on-a-chip. These measures would simplify overall system design, reduce parts count and interface, improve reliability, and reduce cost; and they would meet requirements of systems destined for use in space exploration missions. In this work, the performance of a recently-developed MEMS voltage-controlled oscillator was evaluated under a wide temperature range. Operation of this new commercial-off-the-shelf (COTS) device was also assessed under thermal cycling to address some operational conditions of the space environment
Current capabilities of CubeSats must be improved in order to perform more ambitious missions. Electric propulsion systems will play a key role due to their large specific impulse. Compared to other propulsion alternatives, their simplicity allows an easier miniaturization and manufacturing of autonomous modules into the nano and pico-satellite platform. Pulsed Plasma Thrusters (PPTs) appear as one of the most promising technologies for the near term. The utilization of solid and non-volatile propellants, their low power requirements and their proven reliability in the large scale make them great candidates for rapid implementation. The main challenges are the integration and miniaturization of all the electronic circuitry into a printed circuit board (PCB) that can satisfy the strict requirements that CubeSats present. NASA Ames and the George Washington University have demonstrated functionality and control of three discrete Micro-Cathode Arc Thrusters (CAT) using a bench top configuration that was compatible with the ARC PhoneSat Bus. This demonstration was successfully conducted in a vaccum chamber at the ARC Environmental Test Laboratory. A new effort will integrate a low power Plasma Processing Unit and two plasma thrusters onto a single printed circuit board that will utilize less than 13 U of Bus volume. The target design will be optimized for the accommodation into the PhoneSatEDISON Demonstration of SmallSatellite Networks (EDSN) bus as it uses the same software interface application, which was demonstrated in the previous task. This paper describes the design, integration and architecture of the proposed propulsion subsystem for a planned Technology Demonstration Mission. In addition, a general review of the Pulsed Plasma technology available for CubeSats is presented in order to assess the necessary challenges to overcome further development.
Accurate fault models are required to conduct the experiments defined in validation methodologies for highly reliable fault-tolerant computers (e.g., computers with a probability of failure of 10 to the -9 for a 10-hour mission). Described is a technique by which a researcher can evaluate the capability of the pin-level stuck-at fault model to simulate true error behavior symptoms in very large scale integrated (VLSI) digital circuits. The technique is based on a statistical comparison of the error behavior resulting from faults applied at the pin-level of and internal to a VLSI circuit. As an example of an application of the technique, the error behavior of a microprocessor simulation subjected to internal stuck-at faults is compared with the error behavior which results from pin-level stuck-at faults. The error behavior is characterized by the time between errors and the duration of errors. Based on this example data, the pin-level stuck-at fault model is found to deliver less than ideal performance. However, with respect to the class of faults which cause a system crash, the pin-level, stuck-at fault model is found to provide a good modeling capability.
Josephson junctions are the principal circuit element in numerous superconducting quantum information devices and can be readily integrated into large-scale electronics. However, device integration at the wafer scale necessarily depends on having a reliable, high-fidelity, and high-yield fabrication method for creating Josephson junctions. When creating Al/AlO x based superconducting qubits, the standard Josephson junction fabrication method relies on a sub-micron suspended resist bridge, known as a Dolan bridge, which tends to be particularly fragile and can often times fracture during the resist development process, ultimately resulting in device failure. In this work, we demonstrate a unique Josephson junction lithography mask design that incorporates stress-relief channels. Our simulation results show that the addition of stress-relief channels reduces the lateral stress in the Dolan bridge by more than 70% for all the bridge geometries investigated. In practice, our novel mask design significantly increased the survivability of the bridge during device processing, resulting in 100% yield for over 100 Josephson junctions fabricated.
The High-Luminosity LHC will continue exploring physics beyond the standard model with proton-proton collisions at ten times the luminosity of previous LHC runs. The physics program depends on precise measurements of charged particles near the beams. The CMS experiment will use layers of high-granularity hybrid silicon pixel detectors. Pixelation is achieved by bonding silicon to tiny electrodes, which are directly connected to the specially designed integrated circuit, CROCv2. Pixel detector components are in the pre-production phase, and evaluating prototypes of sensor-chip assemblies from different vendors provides quick feedback and improves reliability during production. This article presents the efforts to test the viability of bare detector assemblies using a manual probe station and electronic charge-injection methods.
Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.
A code trellis is a graphical representation of a code, block or convolutional, in which every path represents a codeword (or a code sequence for a convolutional code). This representation makes it possible to implement Maximum Likelihood Decoding (MLD) of a code with reduced decoding complexity. The most well known trellis-based MLD algorithm is the Viterbi algorithm. The trellis representation was first introduced and used for convolutional codes [23]. This representation, together with the Viterbi decoding algorithm, has resulted in a wide range of applications of convolutional codes for error control in digital communications over the last two decades. There are two major reasons for this inactive period of research in this area. First, most coding theorists at that time believed that block codes did not have simple trellis structure like convolutional codes and maximum likelihood decoding of linear block codes using the Viterbi algorithm was practically impossible, except for very short block codes. Second, since almost all of the linear block codes are constructed algebraically or based on finite geometries, it was the belief of many coding theorists that algebraic decoding was the only way to decode these codes. These two reasons seriously hindered the development of efficient soft-decision decoding methods for linear block codes and their applications to error control in digital communications. This led to a general belief that block codes are inferior to convolutional codes and hence, that they were not useful. Chapter 2 gives a brief review of linear block codes. The goal is to provide the essential background material for the development of trellis structure and trellis-based decoding algorithms for linear block codes in the later chapters. Chapters 3 through 6 present the fundamental concepts, finite-state machine model, state space formulation, basic structural properties, state labeling, construction procedures, complexity, minimality, and sectionalization of trellises. Chapter 7 discusses trellis decomposition and subtrellises for low-weight codewords. Chapter 8 first presents well known methods for constructing long powerful codes from short component codes or component codes of smaller dimensions, and then provides methods for constructing their trellises which include Shannon and Cartesian product techniques. Chapter 9 deals with convolutional codes, puncturing, zero-tail termination and tail-biting.Chapters 10 through 13 present various trellis-based decoding algorithms, old and new. Chapter 10 first discusses the application of the well known Viterbi decoding algorithm to linear block codes, optimum sectionalization of a code trellis to minimize computation complexity, and design issues for IC (integrated circuit) implementation of a Viterbi decoder. Then it presents a new decoding algorithm for convolutional codes, named Differential Trellis Decoding (DTD) algorithm. Chapter 12 presents a suboptimum reliability-based iterative decoding algorithm with a low-weight trellis search for the most likely codeword. This decoding algorithm provides a good trade-off between error performance and decoding complexity. All the decoding algorithms presented in Chapters 10 through 12 are devised to minimize word error probability. Chapter 13 presents decoding algorithms that minimize bit error probability and provide the corresponding soft (reliability) information at the output of the decoder. Decoding algorithms presented are the MAP (maximum a posteriori probability) decoding algorithm and the Soft-Output Viterbi Algorithm (SOVA) algorithm. Finally, the minimization of bit error probability in trellis-based MLD is discussed.
Increased system requirements and functional integration with the aircraft have placed an increased demand on control system capability and reliability. To provide these at an affordable cost and weight and because of the rapid advances in electronic technology, hydromechanical systems are being phased out in favor of digital electronic systems. The transition is expected to be orderly from electronic trimming of hydromechanical controls to full authority digital electronic control. Future propulsion system controls will be highly reliable full authority digital electronic with selected component and circuit redundancy to provide the required safety and reliability. Redundancy may include a complete backup control of a different technology for single engine applications. The propulsion control will be required to communicate rapidly with the various flight and fire control avionics as part of an integrated control concept.
It is important to define and evaluate measures which incorporate most, if not all, of the quantities affecting the overall system reliability. For the simple types of block codes normally employed in space communication systems, the complexity of the encoder and decoder is of little consequence, since the use of integrated circuit technology allows the construction of the basic components in an inexpensive fashion. The complexity is essentially independent of the particular code-decoder used. The processing speed is generally a function of the type of logic used and the technology in the construction of the integrated circuits.
Tabs suitable for electrical or mechanical connections in solar cells and integrated circuits are made by spraying technique. Solder wets copper, copper bonds to aluminum, and aluminum adheres to glass. Arc spraying is automated and integrated with encapsulation, eliminating hand tabbing, improving reliability, and reducing cost.
Current and future requirements of the aerospace sensors and transducers field make it necessary for the design and development of new data acquisition devices and instrumentation systems. New designs are sought to incorporate self-health, self-calibrating, self-repair capabilities, allowing greater measurement reliability and extended calibration cycles. With the addition of power management schemes, state-of-the-art data acquisition systems allow data to be processed and presented to the users with increased efficiency and accuracy. The design architecture presented in this paper displays an innovative approach to data acquisition systems. The design incorporates: electronic health self-check, device/system self-calibration, electronics and function self-repair, failure detection and prediction, and power management (reduced power consumption). These requirements are driven by the aerospace industry need to reduce operations and maintenance costs, to accelerate processing time and to provide reliable hardware with minimum costs. The project's design architecture incorporates some commercially available components identified during the market research investigation like: Field Programmable Gate Arrays (FPGA) Programmable Analog Integrated Circuits (PAC IC) and Field Programmable Analog Arrays (FPAA); Digital Signal Processing (DSP) electronic/system control and investigation of specific characteristics found in technologies like: Electronic Component Mean Time Between Failure (MTBF); and Radiation Hardened Component Availability. There are three main sections discussed in the design architecture presented in this document. They are the following: (a) Analog Signal Module Section, (b) Digital Signal/Control Module Section and (c) Power Management Module Section. These sections are discussed in detail in the following pages. This approach to data acquisition systems has resulted in the assignment of patent rights to Kennedy Space Center under U.S. patent # 6,462,684. Furthermore, NASA KSC commercialization office has issued licensing rights to Circuit Avenue Netrepreneurs, LLC , a minority-owned business founded in 1999 located in Camden, NJ.
Onboard radioisotope power systems being developed and planned for NASA s deep-space missions would require reliable design lifetimes of up to 14 years. Critical components and materials of Stirling convertors have been undergoing extensive testing and evaluation in support of a reliable performance for the specified life span. Of significant importance to the successful development of the Stirling convertor is the design of a lightweight and highly efficient linear alternator. Alternator performance could vary due to small deviations in the permanent magnet properties, operating temperature, and component geometries. Durability prediction and reliability of the alternator may be affected by these deviations from nominal design conditions. Therefore, it is important to evaluate the effect of these uncertainties in predicting the reliability of the linear alternator performance. This paper presents a study in which a reliability-based methodology is used to assess alternator performance. The response surface characterizing the induced open-circuit voltage performance is constructed using 3-D finite element magnetic analysis. Fast probability integration method is used to determine the probability of the desired performance and its sensitivity to the alternator design parameters.
The demand for monolithically integrated photoreceivers based on Si-based technology keeps increasing as low cost and high reliability products are required for the expanding commercial market. Higher speed and wider operating frequency range are expected when SiGe/Si heterojunction is introduced to the circuit design. In this paper, a monolithic SiGe/Si PIN-HBT front-end transimpedance photoreceiver is demonstrated for the first time. For this purpose, mesa-type SiGe/Si PIN-HBT technology was developed. Fabricated HBTs exhibit f(sub max) of 34 GHz with DC gain of 25. SiGe/Si PIN photodiodes, which share base and collector layers of HBTs, demonstrate responsivity of 0.3 A/W at lambda=850 nm and bandwidth of 450 MHz. Based on these devices, single- and dual-feedback transimpedance amplifiers were fabricated and they exhibited the bandwidth of 3.2 GHz and 3.3 GHz with the transimpedance gain of 45.2 dB(Omega) and 47.4 dB(Omega) respectively. Monolithically integrated single-feedback PIN-HBT photoreceivers were implemented and the bandwidth was measured to be approx. 0.5 GHz, which is limited by the bandwidth of PIN photodiodes.