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At least 145 records · Page 8

The Development of Large Inflatable Antenna for Deep-Space Communications

NASA/JPL's deep-space exploration program has been placing emphasis on reducing the mass and stowage volume of its spacecraft's high-gain and large-aperture antennas. To achieve these goals, the concept of deployable flat reflectarray antenna using an inflatable/thin-membrane structure was introduced at JPL several years ago. A reflectarray is a flat array antenna space-fed by a low-gain feed located at its focal point in a fashion similar to that of a parabolic reflector. The ref1ectarray's elements, using microstrip technology, can be printed onto a flat thin-membrane surface and are each uniquely designed to compensate for the different phase delays due to different path lengths from the feed. Although the reflectarray suffers from limited bandwidth (typically < 10%), it offers a more reliably deployed and maintained flat "natural" surface. A recent hardware development at JPL has demonstrated that a 0.2mm rms surface tolerance (l/50th of a wavelength) was achieved on a 3-meter Ka-band inflatable reflectarray. Another recent development, to combat the reflectarray's narrow band characteristic, demonstrated that dual-band performance, such as X- and Ka-bands, with an aperture efficiency of above 50 percent is achievable by the reflectarray antenna. To mechanically deploy the antenna, the reflectarray's thin membrane aperture surface is supported, tensioned and deployed by an inflatable tubular structure. There are several critical elements and challenging issues associated with the inflatable tube structure. First, the inflatable tube must be made rigidizable so that, once the tube is fully deployed in space, it rigidizes itself and the inflation system is no longer needed. In addition, if the tube is penetrated by small space debris, the tube will maintain its rigidity and not cause deformation to the antenna structure. To support large apertures (e.g. 10m or beyond) without causing any buckling to the small-diameter inflatable tube during vibration, the tube, in addition to rigidization, is also reinforced by circumferential thin blades, as well as axial blades. Second, a controlled deployment mechanism, such as by using Velcro strips, must also be implemented into the system so that, for very large structures, the long inflatable tubes can be deployed in a time-controlled fashion and not get tangled with each other. Third, the thermal analysis is another critical element and must be performed for the tube design in order to assure that the inflated tube, under extreme space thermal conditions, will not deform significantly. Finally, the dynamic vibration analysis must also be performed on the inflatable structure. This will investigate the response of the structure due to excitation introduced by the spacecraft maneuvering and thus determine any necessary damping. Several reflectarray antennas have been developed at JPL to demonstrate the technology. These include an earlier 1-meter X-band inflatable reflectarray, a 3-meter Ka-band inflatable reflectarray, a half-meter dual-band (X and Ka) reflectarray, and the current on-going 10-meter inflatable structure development. The detailed RF and mechanical descriptions of these antennas, as well as their performances, will be presented during the conference.

inflatable antenna↗

A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity correction, respectively. The TDC block consumes 97 W at the hit occupancy of 1%. Over a temperature range from 23 C to 78 C and a power supply voltage range from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation-tolerance specifications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

180-GHz Interferometric Imager

A 180-GHz interferometric imager uses compact receiver modules, combined high- and low-gain antennas, and ASIC (application specific integrated circuit) correlator technology, enabling continuous, all-weather observations of water vapor with 25-km resolution and 0.3-K noise in 15 minutes of observation for numerical weather forecasting and tropical storm prediction. The GeoSTAR-II prototype instrument is broken down into four major subsystems: the compact, low-noise receivers; sub-array modules; IF signal distribution; and the digitizer/correlator. Instead of the single row of antennas adopted in GeoSTAR, this version has four rows of antennas on a coarser grid. This dramatically improves the sensitivity in the desired field of view. The GeoSTAR-II instrument is a 48-element, synthetic, thinned aperture radiometer operating at 165-183 GHz. The instrument has compact receivers integrated into tiles of 16 elements in a 4x4 arrangement. These tiles become the building block of larger arrays. The tiles contain signal distribution for bias controls, IF signal, and local oscillator signals. The IF signals are digitized and correlated using an ASIC correlator to minimize power consumption. Previous synthetic aperture imagers have used comparatively large multichip modules, whereas this approach uses chip-scale modules mounted on circuit boards, which are in turn mounted on the distribution manifolds. This minimizes the number of connectors and reduces system mass. The use of ASIC technology in the digitizers and correlators leads to a power reduction close to an order of magnitude.

Kangaslahti, Pekka P.↗

Characterization and Analysis of InGaAsSb Detectors

Profiling of atmospheric CO2 at 2 micron wavelength using the LIDAR technique, has recently gained interest. Although several detectors might be suitable for this application, an ideal device would have high gain, low noise and narrow spectral response peaking around the wavelength of interest. This increases the detector signal-to-noise ratio and minimizes the background signal, thereby increasing the device sensitivity and dynamic range. Detectors meeting the above idealized criteria are commercially unavailable for this particular wavelength. In this paper, the characterization and analysis of Sb-based detectors for 2 micron lidar applications are presented. The detectors were manufactured by AstroPower, Inc., with an InGaAsSb absorbing layer and AlGaAsSb passivating layer. The characterization experiments included spectral response, current versus voltage and noise measurements. The effect of the detectors bias voltage and temperature on its performance, have been investigated as well. The detectors peak responsivity is located at the 2 micron wavelength. Comparing three detector samples, an optimization of the spectral response around the 2 micron wavelength, through a narrower spectral period was observed. Increasing the detector bias voltage enhances the device gain at the narrow spectral range, while cooling the device reduces the cut-off wavelength and lowers its noise. Noise-equivalent-power analysis results in a value as low as 4 x 10(exp -12) W/Hz(exp 1/2) corresponding to D* of 1 x 10(exp 10) cmHz(exp 1/2)/W, at -1 V and 20 C. Discussions also include device operational physics and optimization guidelines, taking into account peculiarity of the Type II heterointerface and transport mechanisms under these conditions.

Abedin, M. Nurul↗

Low frequency electric and magnetic fields

Following preliminary investigations of the low frequency electric and magnetic fields that may exists in the Earth-ionospheric cavity, measurements were taken with state-of-the art spectrum analyzers. As a follow up to this activity, an investigation was initiated to determine sources and values for possible low frequency signal that would appear in the cavity. The lowest cavity resonance is estimated at about 8 Hz, but lower frequencies may be an important component of our electromagnetic environment. The potential field frequencies produced by the electron were investigated by a classical model that included possible cross coupling of the electric and gravitation fields. During this work, an interesting relationship was found that related the high frequency charge field with the extremely low frequency of the gravitation field. The results of numerical calculations were surprisingly accurate and this area of investigation is continuing. The work toward continued development of a standardized monitoring facility is continuing with the potential of installing the prototype at West Virginia State College early in 1990. This installation would be capable of real time monitoring of ELF signals in the Earth-ionoshpere cavity and would provide some directional information. A high gain, low noise, 1/f frequency corrected preamplifier was designed and tested for the ferrite core magnetic sensor. The potential application of a super conducting sensor for the ELF magnetic field detection is under investigation. It is hoped that a fully operational monitoring network could pinpoint the location of ELF signal sources and provide new information on where these signals originate and what causes them, assuming that they are natural in origin.

Spaniol, Craig↗

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

L-band mobile terminal antennas for helicopters

The feasibility of using a low gain antenna (LGA) as a mobile terminal antenna for a helicopter is described in this paper. The objectives are to select the lowest cost antenna system which can be easily mounted on a helicopter and capable of communicating with a satellite, and to determine the best antenna position on the helicopter to mitigate the signal blockage due to rotor blades and the multipath effect from the helicopter's body. The omnidirectional LGA is selected because it is simple, reliable, and low cost. The helix antenna is selected among the many LGA's because it is the most economical one and has the widest elevation beamwidth. Both 2-arm and 4-arm helices are studied experimentally to determine the antenna's performance and the scattering effects from the helicopter's body. It is found that the LGA should be located near the tail section and at least eight inches above the helicopter.

Wu, T. K.↗

Centaur engine gimbal friction characteristics under simulated thrust load

An investigation was performed to determine the friction characteristics of the engine gimbal system of the Centaur upper stage rocket. Because the Centaur requires low-gain autopilots in order to meet all stability requirements for some configurations, control performance (response to transients and limit-cycle amplitudes) depends highly on these friction characteristics. Forces required to rotate the Centaur engine gimbal system were measured under a simulated thrust load of 66,723 N (15,000 lb) and in an altitude/thermal environment. A series of tests was performed at three test conditions; ambient temperature and pressure, ambient temperature and vacuum, and cryogenic temperature and vacuum. Gimbal rotation was controlled, and tests were performed in which rotation amplitude and frequency were varied by using triangular and sinusoidal waveforms. Test data revealed an elastic characteristic of the gimbal, independent of the input signal, which was evident prior to true gimbal sliding. The torque required to initiate gimbal sliding was found to decrease when both pressure and temperature decreased. Results from the low amplitude and low frequency data are currently being used in mathematically modeling the gimbal friction characteristics for Centaur autopilot performance studies.

Askew, J. W.↗

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. Finally, the measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗

NASA Tech Briefs, Februrary 2013

Topics covered include: Measurements of Ultra-Stable Oscillator (USO) Allan Deviations in Space; Gaseous Nitrogen Orifice Mass Flow Calculator; Validation of Proposed Metrics for Two-Body Abrasion Scratch Test Analysis Standards; Rover Low Gain Antenna Qualification for Deep Space Thermal Environments; Automated, Ultra-Sterile Solid Sample Handling and Analysis on a Chip; Measuring and Estimating Normalized Contrast in Infrared Flash Thermography; Spectrally and Radiometrically Stable, Wideband, Onboard Calibration Source; High-Reliability Waveguide Vacuum/Pressure Window; Methods of Fabricating Scintillators With Radioisotopes for Beta Battery Applications; Magnetic Shield for Adiabatic Demagnetization Refrigerators (ADR); CMOS-Compatible SOI MESFETS for Radiation-Hardened DC-to-DC Converters; Silicon Heat Pipe Array; Adaptive Phase Delay Generator; High-Temperature, Lightweight, Self-Healing Ceramic Composites for Aircraft Engine Applications; Treatment to Control Adhesion of Silicone-Based Elastomers; High-Temperature Adhesives for Thermally Stable Aero-Assist Technologies; Rockballer Sample Acquisition Tool; Rock Gripper for Sampling, Mobility, Anchoring, and Manipulation; Advanced Magnetic Materials Methods and Numerical Models for Fluidization in Microgravity and Hypogravity; Data Transfer for Multiple Sensor Networks Over a Broad Temperature Range; Using Combustion Synthesis to Reinforce Berms and Other Regolith Structures; Visible-Infrared Hyperspectral Image Projector; Three-Axis Attitude Estimation With a High-Bandwidth Angular Rate Sensor Change_Detection.m; AGATE: Adversarial Game Analysis for Tactical Evaluation; Ionospheric Simulation System for Satellite Observations and Global Assimilative; Modeling Experiments (ISOGAME); An Extensible, User- Modifiable Framework for Planning Activities; Mission Operations Center (MOC) - Precipitation Processing System (PPS) Interface Software System (MPISS); Automated 3D Damaged Cavity Model Builder for Lower Surface Acreage Tile on Orbiter; Mixed Linear/Square-Root Encoded Single-Slope Ramp Provides Low-Noise ADC with High Linearity for Focal Plane Arrays; RUSHMAPS: Real-Time Uploadable Spherical Harmonic Moment Analysis for Particle Spectrometers; Powered Descent Guidance with General Thrust-Pointing Constraints; X-Ray Detection and Processing Models for Spacecraft Navigation and Timing; and Extreme Ionizing-Radiation-Resistant Bacterium

Source record↗

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗

Resistive AC-Coupled Silicon Detectors: principles of operation and first results from a combined analysis of beam test and laser data

This paper presents the principles of operation of Resistive AC-Coupled Silicon Detectors (RSDs) and measurements of the temporal and spatial resolutions using a combined analysis of laser and beam test data. RSDs are a new type of n-in-p silicon sensor based on the Low-Gain Avalanche Diode (LGAD) technology, where the n+ implant has been designed to be resistive, and the read-out is obtained via AC-coupling. The truly innovative feature of RSD is that the signal generated by an impinging particle is shared isotropically among multiple read-out pads without the need for floating electrodes or an external magnetic field. Careful tuning of the coupling oxide thickness and the n+ doping profile is at the basis of the successful functioning of this device. Several RSD matrices with different pad width-pitch geometries have been extensively tested with a laser setup in the Laboratory for Innovative Silicon Sensors in Torino, while a smaller set of devices have been tested at the Fermilab Test Beam Facility with a 120 GeV/c proton beam. The measured spatial resolution ranges between 2.5μm for 70–100 pad-pitch geometry and 17μm with 200–500 matrices, a factor of 10 better than what is achievable in binary read-out (bin size/12). Beam test data show a temporal resolution of ~40ps for 200 μm pitch devices, in line with the best performances of LGAD sensors at the same gain.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Combined analysis of HPK 3.1 LGADs using a proton beam, beta source, and probe station towards establishing high volume quality control

The upgrades of the CMS and ATLAS experiments for the high luminosity phase of the Large Hadron Collider will employ precision timing detectors based on Low Gain Avalanche Detectors (LGADs). We present a suite of results combining measurements from the Fermilab Test Beam Facility, a beta source telescope, and a probe station, allowing full characterization of the HPK type 3.1 production of LGAD prototypes developed for these detectors. We demonstrate that the LGAD response to high energy test beam particles is accurately reproduced with a beta source. Finally, we further establish that probe station measurements of the gain implant accurately predict the particle response and operating parameters of each sensor, and conclude that the uniformity of the gain implant in this production is sufficient to produce full-sized sensors for the ATLAS and CMS timing detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Investigation of signal characteristics and charge sharing in AC-LGADs with laser and test beam measurements

AC-LGADs, also referred to as resistive silicon detectors, are a recent development of low-gain avalanche detectors (LGADs), based on a sensor design where the multiplication layer and n + contact are continuous, and only the metal layer is patterned. In AC-LGADs, the signal is capacitively coupled from the continuous, resistive n + layer over a dielectric to the metal electrodes. Therefore, the spatial resolution is not only influenced by the electrode pitch, but also the relative size of the metal electrodes. Signal propagation between the metallized areas and charge sharing between electrodes plays a larger role in these detectors than in conventional silicon sensors read out in DC mode. AC-LGADs from two manufacturers were studied in beam tests and with infrared laser scans. The impact of n + layer resistivity and metal electrode pitch on the charge sharing and achievable position resolution is shown. For strips with 100 μm pitch, a resolution of ¡ 5 μm can be reached. Additionally, the charge sharing between neighboring strips is investigated in more detail, indicating the induction of signal charge and subsequent re-sharing over the n + layer. Furthermore, an approach to identify signal sharing over large distances is presented.

47 OTHER INSTRUMENTATION↗

Design and performance of the Fermilab Constant Fraction Discriminator ASIC

Here, we present the design and performance characterization results of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout low gain avalanche detector (LGAD) signals by directly using a constant fraction discriminator (CFD) to measure signal arrival time. Silicon detectors with time resolutions less than 30ps will play a critical role in future collider experiments, and LGADs have been demonstrated to provide the required time resolution and radiation tolerance for many such applications. The FCFD has a specially designed discriminator that is robust against amplitude variations of the signal from the LGAD that normally requires an additional correction step when using a traditional leading edge discriminator. The application of the CFD directly in the ASIC promises to be more reliable and reduces the complication of evolving time-walk corrections throughout the operational lifetime of the detector system. We will present a summary of the measured performance of the FCFD for input signals generated by internal charge injection, LGAD signals from an infrared laser, and LGAD signals from minimum-ionizing particles. The mean time response for LGAD signals with charge ranging between 5 and 26 fC has been measured to vary no more than 10ps, orders of magnitude more stable than an uncorrected leading edge discriminator based measurement, and effectively removes the need for any additional time-walk correction. The measured contribution to the time resolution from the FCFD ASIC is found to be 10ps for signals with charge above 20fC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Signal formation and sharing in AC-LGADs using the ALTIROC 0 front-end chip

The development of detectors that provide high resolution in four dimensions has attracted wide-spread interest in the scientific community for applications in high-energy physics, nuclear physics, medical imaging, mass spectroscopy as well as quantum information. However, finding a technology capable of fulfilling such aspiration proved to be an arduous task. Among other silicon-based candidates, the Low-Gain Avalanche Diode (LGAD) has already shown excellent timing performances but proved to be unsuitable for fine pixelization. Therefore, the AC-coupled LGAD (AC-LGAD) approach was introduced to provide high resolution in both time and space, making it a promising candidate for future 4D detectors. However, appropriate readout electronics must be developed to match the sensor's fast-time and fine-pitch capabilities. This is currently a major technological challenge. Here, we test AC-LGAD prototypes read out by the fast-time ASIC ALTIROC 0, originally developed for the readout of DC-coupled LGADs for the ATLAS experiment at the High Luminosity-LHC. Signal generated by either betas from a 90 Sr source or a focused infra-red laser were analyzed. This paper details the first successful readout of an AC-LGAD sensor using a readout chip. This result will pave the way for the design and construction of a new generation of AC-LGAD-based 4D detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗