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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Design, development and flight test of a demonstration advanced avionics system

The design of integrated avionics suitable for general aviation was examined. The program emphasizes the use of data busing, distributed microprocessors, shared electronic displays and data entry devices, and improved functional capability. Design considerations includes cost, reliability, maintainability, and modularity. A demonstration advanced avionics system (DAAS) was designed, built, and flight tested in a Cessna 402, twin engine, general aviation aircraft. The DAAS, and the system architecture are described.

Denery, D. G.↗
NASA NTRS1977

A programmable microcomputer for real time speech processing

The implementation of a programmable microprocessor for real time speech processing is described. The design of a fast special-purpose computer operating at 150 nsec per instruction time reduces the problem of speech encoding and decoding to a software problem. Each instruction is a twelve-bit word, and the information conveyed by a word is explained. The microprocessor is controlled by two clocks - the A/D clock, or input sampling clock, which loads the digital input into the input register and presets the counter to a value set by the external switches; and the instruction clock, or system clock, which operates at 6 MHz. At this system clock rate and a sampling clock rate of 30 KHz, 200 instructions can be executed between samples, and for many speech encoding and decoding algorithms, 200 instructions are more than enough. The microcomputer is being used to test various delta modulator encoding algorithms.

Apelewicz, T.↗
NASA NTRS1991

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Srivas, Mandayam↗
NASA NTRS1991

Hyperswitch communication network

The Hyperswitch Communication Network (HCN) is a large scale parallel computer prototype being developed at JPL. Commercial versions of the HCN computer are planned. The HCN computer being designed is a message passing multiple instruction multiple data (MIMD) computer, and offers many advantages in price-performance ratio, reliability and availability, and manufacturing over traditional uniprocessors and bus based multiprocessors. The design of the HCN operating system is a uniquely flexible environment that combines both parallel processing and distributed processing. This programming paradigm can achieve a balance among the following competing factors: performance in processing and communications, user friendliness, and fault tolerance. The prototype is being designed to accommodate a maximum of 64 state of the art microprocessors. The HCN is classified as a distributed supercomputer. The HCN system is described, and the performance/cost analysis and other competing factors within the system design are reviewed.

Peterson, J.↗
NASA NTRS2008

An Overview of Starfish: A Table-Centric Tool for Interactive Synthesis

Engineering is an interactive process that requires intelligent interaction at many levels. My thesis [1] advances an engineering discipline for high-level synthesis and architectural decomposition that integrates perspicuous representation, designer interaction, and mathematical rigor. Starfish, the software prototype for the design method, implements a table-centric transformation system for reorganizing control-dominated system expressions into high-level architectures. Based on the digital design derivation (DDD) system a designer-guided synthesis technique that applies correctness preserving transformations to synchronous data flow specifications expressed as co- recursive stream equations Starfish enhances user interaction and extends the reachable design space by incorporating four innovations: behavior tables, serialization tables, data refinement, and operator retiming. Behavior tables express systems of co-recursive stream equations as a table of guarded signal updates. Developers and users of the DDD system used manually constructed behavior tables to help them decide which transformations to apply and how to specify them. These design exercises produced several formally constructed hardware implementations: the FM9001 microprocessor, an SECD machine for evaluating LISP, and the SchemEngine, garbage collected machine for interpreting a byte-code representation of compiled Scheme programs. Bose and Tuna, two of DDD s developers, have subsequently commercialized the design derivation methodology at Derivation Systems, Inc. (DSI). DSI has formally derived and validated PCI bus interfaces and a Java byte-code processor; they further executed a contract to prototype SPIDER-NASA's ultra-reliable communications bus. To date, most derivations from DDD and DRS have targeted hardware due to its synchronous design paradigm. However, Starfish expressions are independent of the synchronization mechanism; there is no commitment to hardware or globally broadcast clocks. Though software back-ends for design derivation are limited to the DDD stream-interpreter, targeting synchronous or real-time software is not substantively different from targeting hardware.

Tsow, Alex↗
NASA NTRS1983

Development history of the Hybrid Test Vehicle

Phase I of a joint Department of Energy/Jet Propulsion Laboratory Program undertook the development of the Hybrid Test Vehicle (HTV), which has subsequently progressed through design, fabrication, and testing and evaluation phases. Attention is presently given to the design and test experience gained during the HTV development program, and a discussion is presented of the design features and performance capabilities of the various 'mule' vehicles, devoted to the separate development of engine microprocessor control, vehicle structure, and mechanical components, whose elements were incorporated into the final HTV design. Computer projections of the HTV's performance are given.

Trummel, M. C.↗
NASA NTRS1997

A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.

Fang, Wai-Chi↗
DOE OSTI2026

Development and Evaluation of a Cost-Effective Behind-the-Meter Synchronized Measurement Unit for Enhanced Grid Integration

This paper presents the development of the Inverter Based Resource Monitor (IBRM), an innovative behind-the-meter synchronized measurement unit (SMU) tailored for integration with inverter-based resources (IBRs). The IBRM distinguishes itself as a highly accurate and cost-effective SMU, offering facile deployment and connectivity to IBRs. It is equipped to conduct real-time voltage and current waveform analyses, serving as a phasor measurement unit (PMU) with exceptionally rapid synchrophasor transmission capabilities. The device incorporates a cutting-edge dual-core architecture designed to minimize sampling delays inherent to its microprocessor, thereby enhancing the precision of synchronized waveform measurements. Moreover, the IBRM is adept at recording high-fidelity waveform data, capturing nuances such as waveform distortions, high-order harmonics, and wide-band oscillations prevalent in power grids with substantial IBR presence. A prototype of the IBRM has been constructed and subjected to rigorous testing to assess its functional capabilities and measurement precision, utilizing both idealized signal generators and a real-world off-grid inverter setup as benchmarks.

Wu, Ori [ORNL] (ORCID:0000000326723410)↗
NASA NTRS1980

Analysis of SETI data collected in the parasitic mode

A system for performing SETI observations continuously as part of non-SETI observations at a radio observatory is presented, and the analysis of results obtained by the parasitic system is discussed. The system, designated SERENDIP, is a real-time microprocessor-controlled spectrum analyzer with algorithms for performing statistical operations and recording those spectra with characteristics presumed to be typical of intelligent rather than astrophysical origin. Programs also exist for the post-acquisition analysis of signal autocorrelation, power spectra, time behavior and positional coordinates, and for a generalized cluster analysis to detect clusters of signal detections. In a recent run of 35 days, the SERENDIP system detected 4000 narrowband spectra exceeding a preset threshold, of which 98% were determined to be of instrumental origin. The remaining class of detections is also believed to be instrumental, although not as well organized as the first signals, and means are currently being sought for eliminating them.

Bowyer, S.↗
NASA NTRS1998

A Review of Microgravity Levels on Ten OARE Shuttle Missions

The Orbital Acceleration Research Experiment (OARE) is an accelerometer package with nano-g sensitivity and on-orbit bias calibration capabilities. The OARE consists of a three axis miniature electrostatic accelerometer (MESA), a full in-flight bias and scale factor calibration station, and an on-board microprocessor for experiment control and data storage. Originally designed to measure and record the aerodynamic acceleration environment of the NASA Space Shuttles during re-entry, the OARE has been used on ten shuttle missions to measure the quasi-steady acceleration environment (<1 Hz) of the Orbiter while in low-Earth orbit. The effects on the quasi-steady acceleration environment from Orbiter systems, Orbiter attitude, Orbiter altitude, and crew activity are well understood as a result of these ten shuttle missions. This knowledge of the quasi-steady acceleration realm has direct application to understanding the quasi-steady acceleration environment expected for the International Space Station (ISS). This paper will summarize the more salient aspects of this quasi-steady acceleration knowledge base.

McPherson, Kevin M.↗
NASA NTRS2006

A Low Noise, Microprocessor-Controlled, Internally Digitizing Rotating-Vane Electric Field Mill for Airborne Platforms

This paper reports on a new generation of aircraft-based rotating-vane style electric field mills designed and built at NASA's Marshall Spaceflight Center. The mills have individual microprocessors that digitize the electric field signal at the mill and respond to commands from the data system computer. The mills are very sensitive (1 V/m per bit), have a wide dynamic range (115 dB), and are very low noise (+/-1 LSB). Mounted on an aircraft, these mills can measure fields from +/-1 V/m to +/-500 kV/m. Once-per-second commanding from the data collection computer to each mill allows for precise timing and synchronization. The mills can also be commanded to execute a self-calibration in flight, which is done periodically to monitor the status and health of each mill.

Bateman, M. G.↗
NASA NTRS2015

2nd Generation QUATARA Flight Computer Project

Single core flight computer boards have been designed, developed, and tested (DD&T) to be flown in small satellites for the last few years. In this project, a prototype flight computer will be designed as a distributed multi-core system containing four microprocessors running code in parallel. This flight computer will be capable of performing multiple computationally intensive tasks such as processing digital and/or analog data, controlling actuator systems, managing cameras, operating robotic manipulators and transmitting/receiving from/to a ground station. In addition, this flight computer will be designed to be fault tolerant by creating both a robust physical hardware connection and by using a software voting scheme to determine the processor's performance. This voting scheme will leverage on the work done for the Space Launch System (SLS) flight software. The prototype flight computer will be constructed with Commercial Off-The-Shelf (COTS) components which are estimated to survive for two years in a low-Earth orbit.

Falker, Jay↗
NASA NTRS1980

Microprocessor realizations of range and range-rate filters in radar systems

This paper describes the implementation of digital radar range-rate filters on a microprocessor-based system. A range-rate filter processes a digitized noisy range signal to recover smoothed range data and its derivative, range rate. Two filter designs are implemented. Considerations aiding their efficient operation on an 8-bit microprocessor are discussed. The filters are subjected to a noisy range input signal of known variance, and the associated output signals are statistically analysed to determine noise-rejection characteristics. These results are compared to analytical predictions.

Fleischer, D.↗
NASA NTRS2016

Advanced EVA Suit Camera System Development Project

The National Aeronautics and Space Administration (NASA) at the Johnson Space Center (JSC) is developing a new extra-vehicular activity (EVA) suit known as the Advanced EVA Z2 Suit. All of the improvements to the EVA Suit provide the opportunity to update the technology of the video imagery. My summer internship project involved improving the video streaming capabilities of the cameras that will be used on the Z2 Suit for data acquisition. To accomplish this, I familiarized myself with the architecture of the camera that is currently being tested to be able to make improvements on the design. Because there is a lot of benefit to saving space, power, and weight on the EVA suit, my job was to use Altium Design to start designing a much smaller and simplified interface board for the camera's microprocessor and external components. This involved checking datasheets of various components and checking signal connections to ensure that this architecture could be used for both the Z2 suit and potentially other future projects. The Orion spacecraft is a specific project that may benefit from this condensed camera interface design. The camera's physical placement on the suit also needed to be determined and tested so that image resolution can be maximized. Many of the options of the camera placement may be tested along with other future suit testing. There are multiple teams that work on different parts of the suit, so the camera's placement could directly affect their research or design. For this reason, a big part of my project was initiating contact with other branches and setting up multiple meetings to learn more about the pros and cons of the potential camera placements we are analyzing. Collaboration with the multiple teams working on the Advanced EVA Z2 Suit is absolutely necessary and these comparisons will be used as further progress is made for the overall suit design. This prototype will not be finished in time for the scheduled Z2 Suit testing, so my time was also spent creating a case for the original interface board that is already being used. This design is being done by use of Creo 2. Due to time constraints, I may not be able to complete the 3-D printing portion of this design, but I was able to use my knowledge of the interface board and Altium Design to help in the task. As a side project, I assisted another intern in selecting and programming a microprocessor to control linear actuators. These linear actuators will be used to move various increments of polyethylene for controlled radiation testing. For this, we began the software portion of the project using the Arduino's coding environment to control an Arduino Due and H-Bridge components. Along with the obvious learning of computer programs such as Altium Design and Creo 2, I also acquired more skills with networking and collaborating with others, being able to multi-task because of responsibilities to work on various projects, and how to set realistic goals in the work place. Like many internship projects, this project will be continued and improved, so I also had the chance to improve my organization and communication skills as I documented all of my meetings and research. As a result of my internship at JSC, I desire to continue a career with NASA, whether that be through another internship or possibly a co-op. I am excited to return to my university and continue my education in electrical engineering because of all of my experiences at JSC.

Mock, Kyla↗
NASA NTRS1984

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

Advanced composite aircraft designs include fault-tolerant computer-based digital control systems with thigh reliability requirements for adverse as well as optimum operating environments. Since aircraft penetrate intense electromagnetic fields during thunderstorms, onboard computer systems maya be subjected to field-induced transient voltages and currents resulting in functional error modes which are collectively referred to as digital system upset. A methodology was developed for assessing the upset susceptibility of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general-purpose microprocessor were studied via tests which involved the random input of analog transients which model lightning-induced signals onto interface lines of an 8080-based microcomputer from which upset error data were recorded. The application of Markov modeling to upset susceptibility estimation is discussed and a stochastic model development.

Belcastro, C. M.↗
NASA NTRS1977

Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

Source record↗
NASA NTRS1978

Implementation of real-time digital signal processing systems

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Narasimha, M.↗
NASA NTRS1976

Distributed microprocessors for spacecraft control and data handling

The Unified Data System (UDS) group at JPL is attempting to reduce total mission costs by designing a spacecraft data system which takes advantage of the natural and historical partitioning of a spacecraft into subsystems. Each subsystem is assigned a microprocessor which needs just enough capability to control the sensors and actuators of that subsystem, collect its data and maintain time synchronization with the rest of the spacecraft. The resulting distributed system avoids many of the overhead costs of a single centralized multi-processing system. To minimize complexity and therefore minimize total mission costs, a variety of standards and restrictions are imposed on the design of hardware, software, and communications. Articulation of these standards and restrictions is a major benefit deriving from the UDS program.

Lesh, F.↗