A low drive material for monolithic ferrite memories
Low drive material for monolithic ferrite memories
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Low drive material for monolithic ferrite memories
Breadboard models and logic design of monolithic parallel processor
Precision monolithic circuits fabrication techniques, describing differential amplifier design incorporating emitter feedback and direct DC errors compensation
Selective gold diffusion on monolithic silicon chips for switching and nonswitching amplifier devices and circuits and linear and digital logic circuits
Combination of complementary MOS and complementary bipolar circuits on monolithic silicon chip
Monolithic amplifier incorporating vertical n-p-n and lateral p-n-p transistor structures
Improved test standards for monolithic circuits, and effects of oxide edge profile, aluminum deposition, and sintering process on microcrack formation
Research and developments of monolithic, MOS, ten bit, analog to digital converter
Monolithic precision castings using photoetched plastic and lost-wax investment techniques
Two new processes form complementary transistors in monolithic semiconductor circuits, require fewer steps /infusions/ than previous methods, and eliminate such problems as nonuniform h sub FE distribution, low yield, and large device formation.
Development of flexible selected interconnection technique for monolithic circuits
Monolithic COS/MOS large scale parallel processor array
Design and tests of monolithic catalyst beds for monopropellant hydrazine reactors
Substrate emitter monolithic inverted transistor structure for low-power high-current gain application
The theory and design criteria for monolithic, two-junction cascade solar cells are described. The departure from the conventional solar cell analytical method and the reasons for using the integral form of the continuity equations are briefly discussed. The results of design optimization are presented. The energy conversion efficiency that is predicted for the optimized structure is greater than 30% at 300 K, AMO and one sun. The analytical method predicts device performance characteristics as a function of temperature. The range is restricted to 300 to 600 K. While the analysis is capable of determining most of the physical processes occurring in each of the individual layers, only the more significant device performance characteristics are presented.
Surface acoustic waves excited in a Si-SiO2-ZnO layered structure can produce a traveling electric field in the silicon substrate. Charges stored in the traveling potential wells can be transferred at high speed and density and with less complexity. The monolithic structure under investigation for the SAW-charge transfer device consists of a silicon substrate, a thin silicon dioxide insulating layer on top of which a ZnO piezoelectric film is deposited by sputtering. The surface acoustic waves are excited by interdigital transducers. The signal charge is injected into traveling potential wells that travel with the velocity of sound. Conditions for the transfer of the charges by the traveling wells are analyzed. A surface acoustic wave program was used to determine the optimum structure dimensions and transducer configuration which will produce the highest coupling in the excitation of the piezoelectric waves.
Circuit is self-biasing, with differential current-to-voltage conversion. CMOS current-differencing readout consists of dc-balanced pair of virtual ground stages and current-differencing circuit similar to circuit mirror. Triode multiplier cell replaces test sources to form monolithic configuration. Transistors belonging to selected multiplier cell need to be duplicated for each multiplier within correlator chip. Remaining elements form part of readout and may be scaled as single common readout stage.
The paper presents the Multiwavelength Monolithic Integrated Fiber Optic Terminal (MMIFOT) developed under NASA sponsorship. The program aims to utilize the advantage of optical fiber and integrated optical device technology to achieve parallel transmission of many data channels over the same optical fiber link, and to develop an eight channel wavelength multiplexed fiber optic link that transmits eight bit words in a parallel format at a nominal rate of 20 Mw/s; in the second phase of the program a transmitter/multiplexer chip will be developed. The MMIFOT configuration, the receiver/demultiplexer development, and the waveguide detector development are discussed, concluding that the first phase of the MMIFOT program will culminate in the demonstration of an eight channel receiver/demultiplexer chip with a four channel breadboard multiplexer with the data rate of 20 Mbps per channel with a dynamic range of minimum 20 dB.