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Results for “nonvolatile memory”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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144 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Kelvin Probe Force Microscopy Imaging of Plasticity in Hydrogenated Perovskite Nickelate Multilevel Neuromorphic Devices

Ion drift in nanoscale electronically inhomogeneous semiconductors is among the most important mechanisms being studied for designing neuromorphic computing hardware. However, nondestructive imaging of the ion drift in operando devices directly responsible for multiresistance states and synaptic memory represents a formidable challenge. Here, we present Kelvin probe force microscopy imaging of hydrogen-doped perovskite nickelate device channels subject to high-speed electric field pulses to directly visualize proton distribution by monitoring surface potential changes spatially, which is also supported with finite element-based electric field distribution studies. First-principles calculations provide mechanistic insights into the origin of surface potential changes as a function of hydrogen donor doping that serves as the contrast mechanism. We demonstrate 128 (7-bit) nonvolatile conductance levels in such devices relevant to in-memory computing applications. The synaptic plasticity measurements are implemented in spiking neural networks and show promising results for classification (SciKit Learn’s Iris and Wine data sets) and control (OpenAI’s CartPole-v1 and BipedalWalker-v3) simulation tasks.

Kelvin probe force microscopy↗
NASA NTRS1990

Programmable synaptic devices for electronic neural nets

The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

Moopenn, A.↗
DOE OSTI2024

Variation Tolerant and Energy-Efficient Charge Domain Compute-in-Memory Array with Binary and Multi-Level Cell Ferroelectric FET

Here, in this work, we present a variation-tolerant and energy-efficient charge-domain Ferroelectric FET (FeFET) based Compute-in-Memory (CiM) array design that is compatible with both binary and multi-level cell memory sensing. We demonstrate that: 1) by exploiting FeFET as a nonvolatile switch, its high ON/OFF ratio in the subthreshold region can suppress the error introduced by the inaccurate ON state conductance, thus realizing robust CiM operations, unlike the current-domain CiM design where the computation results is highly sensitive to the device conductance variation; 2) by leveraging a dense dynamic random access memory (DRAM)-like 1FeFET1C cell structure, the proposed design benefits from the existing high density DRAM establishment while also significantly relaxing the capacitor retention and transistor leakage requirement; 3) the charge-domain CiM supports both binary FeFET with minimum overhead and MLC FeFET with tolerable latency for MLC state sensing, whose efficacy is validated experimentally on both cell-level and array-level; 4) the proposed CiM shows much better device variation resilience than conventional current-domain CiM, and also improves inference accuracy. Macro-level evaluation results demonstrate significantly higher energy efficiency and area efficiency compared to prior CiM works.

Duan, Jiahui [University of Notre Dame, IN (United↗
NASA NTRS1990

Solid-state thin-film memistor for electronic neural networks

This paper reports on a tungsten-oxide-based, nonvolatile, electrically reprogrammable, variable resistance device as an analog synaptic memory connection for electronic neural networks. A voltage controlled, reversible injection of H(+) ions in electrochromic thin films of WO3 is utilized to modulate its resistance. A hygroscopic thin film of Cr2O3 is the source of H(+) ions. The resistance of the device can be tailored and stabilized over a wide dynamic range (about 4 orders of magnitude), and the programming speed is modulated by the control voltage. The suitability of such a device in terms of its response speed, reversibility, stability, and cyclability for its use in electronic neural networks is discussed.

Thakoor, S.↗
NASA NTRS1994

Three-Dimensional Vertical-Bloch-Line Memory System

In proposed magnetic memory system without moving parts, data is stored in stack of two-dimensional vertical-Bloch-line (VBL) memory chips or modules. System similar to one described in "Three-Dimensional Magnetic-Bubble Memory System" (NPO-18533). Each VBL module in this memory system silimar to module described in "Vertical-Bloch-Line Memory" (NPO-18467). Advantages include high storage density, high speed, nonvolatility, and insensitivity to ionizing radiation.

Katti, Romney R.↗
NASA NTRS1991

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗
NASA NTRS1995

Garnet Random-Access Memory

Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

Katti, Romney R.↗
DOE OSTI2026

Inductance meets memory in a quantum magnet

Orbital degrees of freedom offer a largely untapped route to emergent dynamical phenomena in correlated quantum materials. However, it remains unclear whether collective orbital states can intrinsically generate both reactive and memory functionalities in a bulk system. Here we show that in the ferrimagnet Mn₃Si₂Te₆, nonequilibrium reconfiguration of chiral orbital currents produces both emergent inductance and nonvolatile memristance as intrinsic properties of a single crystal. At low frequency and under a magnetic field along the c axis, coherent orbital-current domains generate robust clockwise inductive I-V loops. At higher frequency and low field, current-driven first-order reconfiguration leads to incomplete reversal and metastable trapping, producing an intrinsic electromotive force and a finite remanent voltage at zero current. These results establish orbital currents as a class of quantum state variables that encode both reactive and memory functionalities, opening routes toward intrinsically reconfigurable and energy-efficient electronic systems.

Cao, Tristan [University of Colorado, Boulder]↗
NASA NTRS1978

A solid state data recorder for spacecraft telemetry applications

A solid state data recorder (SSDR) has been developed which offers a high-reliability alternative to tape recorders in many spacecraft telemetry applications. The storage medium used in this recorder was ferrimagnetic garnet films supporting nonvolatile magnetic bubble domains. The recorder was designed using modular construction consisting of a digital control unit, power supply, and two memory modules. A prototype SSDR has been fabricated which is designed for 100-million bits of storage but was populated with 128 chips for a 13-million bit capacity. Preliminary tests indicate satisfactory operation.

Stermer, R. L., Jr.↗
NASA NTRS1991

Magnetic Analog Random-Access Memory

Proposed integrated, solid-state, analog random-access memory base on principle of magnetic writing and magnetoresistive reading. Current in writing conductor magnetizes storage layer. Remanent magnetization in storage layer penetrates readout layer and detected by magnetoresistive effect or Hall effect. Memory cells are part of integrated circuit including associated reading and writing transistors. Intended to provide high storage density and rapid access, nonvolatile, consumes little power, and relatively invulnerable to ionizing radiation.

Katti, Romney R.↗
NASA NTRS1993

Nonvolatile Array Of Synapses For Neural Network

Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.

Tawel, Raoul↗
DOE OSTI2025

Magnetic Switching in Monolayer 2D Diluted Magnetic Semiconductors via Spin‐to‐Spin Conversion

Abstract The integration of 2D van der Waals (vdW) magnets with topological insulators or heavy metals holds great potential for realizing next‐generation spintronic memory devices. However, achieving high‐efficiency spin–orbit torque (SOT) switching of monolayer vdW magnets at room temperature poses a significant challenge, particularly without an external magnetic field. Here, it is shown field‐free, deterministic, and nonvolatile SOT switching of perpendicular magnetization in the monolayer, diluted magnetic semiconductor (DMS), Fe‐doped MoS 2 (Fe:MoS 2 ) at up to 380 K with a current density of ≈7 × 10 4 A cm −2 . The in situ doping of Fe into monolayer MoS 2 via chemical vapor deposition and the geometry‐induced strain in the crystal break the rotational switching symmetry in Fe:MoS 2 , promoting field‐free SOT switching by generating out‐of‐plane spins via spin‐to‐spin conversion. An apparent anomalous Hall effect (AHE) loop shift at a zero in‐plane magnetic field verifies the existence of z spins in Fe:MoS 2 , inducing an antidamping‐like torque that facilitates field‐free SOT switching. This field‐free SOT application using a 2D ferromagnetic monolayer provides a new pathway for developing highly power‐efficient spintronic memory devices.

Chen, Siwei [Department of Mechanical Engineering ↗
DOE OSTI2024

Twist-assisted all-antiferromagnetic tunnel junction in the atomic limit

Abstract Antiferromagnetic spintronics 1,2 shows great potential for high-density and ultrafast information devices. Magnetic tunnel junctions (MTJs), a key spintronic memory component that are typically formed from ferromagnetic materials, have seen rapid developments very recently using antiferromagnetic materials 3,4 . Here we demonstrate a twisting strategy for constructing all-antiferromagnetic tunnel junctions down to the atomic limit. By twisting two bilayers of CrSBr, a 2D antiferromagnet (AFM), a more than 700% nonvolatile tunnelling magnetoresistance (TMR) ratio is shown at zero field (ZF) with the entire twisted stack acting as the tunnel barrier. This is determined by twisting two CrSBr monolayers for which the TMR is shown to be derived from accumulative coherent tunnelling across the individual CrSBr monolayers. The dependence of the TMR on the twist angle is calculated from the electron-parallel momentum-dependent decay across the twisted monolayers. This is in excellent agreement with our experiments that consider twist angles that vary from 0° to 90°. Moreover, we also find that the temperature dependence of the TMR is, surprisingly, much weaker for the twisted as compared with the untwisted junctions, making the twisted junctions even more attractive for applications. Our work shows that it is possible to push nonvolatile magnetic information storage to the atomically thin limit.

Science & Technology - Other Topics↗
DOE OSTI2026

Heteroepitaxial control of thickness, strain, and domain architecture in few-layer ferroelectric tin monochalcogenides

Thin-film epitaxy and epitaxial strain have been widely exploited to tune domain configurations, switching behavior, and ferroic properties in conventional three-dimensional ferroelectric thin films; however, its application to controlling the properties of two-dimensional (2D) ferroelectrics has remained largely unexplored. Here, using SnX (X = Se, S) as a model system, we demonstrate heteroepitaxial control of thickness, strain state, and domain architecture in few-layer ferroelectric SnX via growth on monolayer MoS2 van der Waals (vdW) templates. Compared with conventional growth, MoS2-templated heteroepitaxy promotes epitaxial alignment, yielding ultrathin SnSe films with improved crystalline quality, full areal coverage, and enlarged lateral dimensions. Strong interfacial epitaxial coupling induces pronounced in-plane strain and stabilizes a hierarchical ferroelastic domain architecture, in which long-range 90° stripe domains are further subdivided into nanoscale rotational variants, as revealed by scanning transmission electron microscopy and synchrotron X-ray microscopy. Piezoresponse force microscopy and second-harmonic polarimetry confirm robust in-plane polarization, while ferroelectricity in SnSe is established through polarization-electric field hysteresis and nonvolatile ferroelectric resistive switching with on/off ratios approaching 1000. A nonvolatile, switchable ferroelectric diode effect further evidences direct coupling between polarization and charge transport. Notably, ferroelectric switchability exhibits a strong thickness dependence and is preserved only below ∼10 layers. This vdW heteroepitaxial strategy is further extended to ferroelectric SnS. The seamless heteroepitaxial integration of 2D ferroelectrics with CMOS-compatible, wafer-scale MoS2 templates provides a general and scalable route for strain-enabled structural and ferroelectric engineering in emerging memory and low-power optoelectronic applications.

Wang, Yueyin↗
NASA NTRS1995

Maximum Acceleration Recording Circuit

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Bozeman, Richard J., Jr.↗
DOE OSTI2025

Dual-ion ECRAM as a stable and accurate analog synapse

Electrochemical random-access memory (ECRAM) works by tuning the bulk electronic conductance of functional materials via reversible, electrochemical insertion of ions, resulting in stable analog resistive switching, attractive for analog in-memory and neuromorphic computing. However, achieving fast programming for training and long retention for inference has been elusive. Protonic ECRAM demonstrates fast programming but insufficient retention, while oxygen-based ECRAM with excellent retention requires elevated programming temperatures. Cu-based ECRAM offers a compromise, with an activation energy (E A ) of ≈0.76 eV between protons (E A ≈ 0.4 eV) and oxygen (E A > 1 eV), enabling extensive retention and room temperature programming. Combining Cu 2+ ions with protons to form a dual-ion ECRAM, we demonstrate two distinct switching behaviors: fast switching at ≤5 V, (E A ≈ 0.45 eV) via protons, and nonvolatile, room temperature switching at ≥8 V, with E A ≈ 0.76 eV via Cu 2+ ions. In conclusion, the Cu-based state exhibits a wide conductance range, with excellent retention, low noise, and linear current-voltage behavior, achieving digital-equivalent ImageNet inference accuracy.

analog in-memory computing↗
NASA NTRS2003

Radiation effects on microelectronics and future space missions

This paper briefly reviews the three basic radiation effect mechanisms, and how they interrupt the functionality of currently available non-volatile memory technologies. This paper also presents a very general overview of the radiation environments expected in future space exploration missions. Unfortunately, these environments will be very harsh, from a radiation standpoint, and thus a significant effort is required to develop non-volatile technologies that will meet future mission requirements.

radiation effects↗
NASA NTRS2000

All-Metal Magnetic RAM

The factors that enter into the development of an all-metal, nonvolatile magnetic RAM, in which multilayer giant magnetoresistive films are used for all functions - storage, readout, and support electronics - are described. Four significant characteristics are expected to favor all-metal over hybrid magnetic RAM. First, silicon-technology fabrication requires a large number of masking steps, including complex ones such as ion implantation. Conversely, all-metal technology is inherently simple: fewer masking steps, no doping, scaling to lithographic limits, very little operating power. Second, the all-metal footprint is significantly smaller than the hybrid one. Third, an all-metal RAM is expected to be able to be miniaturized to lithographic limits; miniaturization of hybrid magnetic RAMs is likely to be limited by the semiconductor circuitry. Finally, semiconductor processing and magnetic processing in MRAM are done separately because the former requires high temperatures, whereas magnetic fabrication is a low-temperature process. By contrast, because both GMR electronics and the memory elements are made of the same materials, the two major components are deposited and patterned concurrently on the same substrate.

Torok, E. J.↗