Search NASA⌕ Search

SEARCH · Search NASA

Results for “transistor scaling”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

High Power SiGe X-Band (8-10 GHz) Heterojunction Bipolar Transistors and Amplifiers

Limited by increased parasitics and thermal effects as the device size becomes large, current commercial SiGe power HBTs are difficult to operate at X-band (8-12 GHz) with adequate power added efficiencies at high power levels. We found that, by changing the heterostructure and doping profile of SiGe HBTs, their power gain can be significantly improved without resorting to substantial lateral scaling. Furthermore, employing a common-base configuration with proper doping profile instead of a common-emitter configuration improves the power gain characteristics of SiGe HBTs, which thus permits these devices to be efficiently operated at X-band. In this paper, we report the results of SiGe power HBTs and MMIC power amplifiers operating at 8-10 GHz. At 10 GHz, 22.5 dBm (178 mW) RF output power with concurrent gain of 7.32 dB is measured at the peak power-added efficiency of 20.0% and the maximum RF output power of 24.0 dBm (250 mW) is achieved from a 20 emitter finger SiGe power HBT. Demonstration of single-stage X-band medium-power linear MMIC power amplifier is also realized at 8 GHz. Employing a 10-emitter finger SiGe HBT and on-chip input and output matching passive components, a linear gain of 9.7 dB, a maximum output power of 23.4 dBm and peak power added efficiency of 16% is achieved from the power amplifier. The MMIC exhibits very low distortion with third order intermodulation (IM) suppression C/I of -13 dBc at output power of 21.2 dBm and over 20dBm third order output intercept point (OIP3).

Ma, Zhenqiang↗
NASA NTRS1991

Single board system for fuzzy inference

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Symon, James R.↗
DOE OSTI2020

An Experimental Feasibility Study on Applying Neutron Tomography to Encapsulated Spent Nuclear Fuel - 20050

Visual inspection makes easier to ensure the integrity and safety of spent nuclear fuel (SNF) than any classical techniques. Various classical techniques have been applied but there are no reliable methods to qualitatively and quantitatively verify spent fuel in dry storage. Thus, the present authors have developed the prototype safeguards apparatus for dry storage employing the array of He-4 gas scintillation detectors (S670E, Arktis Radiation Detectors Ltd., Switzerland), newly designed to simultaneously measure thermal and fast neutrons without any moderators. The S670E detector has a cylindrical shape with a diameter of 52 mm and active length of 600 mm (total length: 875 mm). The detector is filled by He-4 gas with an approximate pressure of 180 bar for fast neutron detection, and its inner wall is coated by Li-6 for thermal neutron detection. The scintillation lights generated via Li-6 nuclear reaction and elastic scattering are collected by 24 SiPMs linearly paired at the center of the detector. The detector delivers a TTL (Transistor-Transistor Logic) output for pulse readout and UART (Universal Asynchronous Receiver Transmitter) for device control. In order to assess feasibility of the apparatus, an experimental system has been designed, built, and optimized via computational studies. Cf-252 neutron sources and linearly arrayed detectors, working as a single detector, were occupied for this study due to the difficulties in working with SNF. The laboratory scale cask (diameter: 0.67 m, height: 1.5 m), minimized by a factor of 10 compared to the actual thickness of a commercial TN-32 cask, was also manufactured. The detector array was designed to rotate the lab-scale cask and obtain 36 image profiles at every 10 degrees. All profiles were aligned in single frame image called a sinogram, and the cross-sectional image was then fabricated by the inverse radon transform algorithm. These experiments have been repeated with different configurations and numbers of sources. Some gamma-ray sources were also measured with neutron sources in order to distinguish between neutron and gamma-ray pulses. Basically, a He-4 detector is designed to run on Linux OS so it is difficult to directly apply to Windows-based equipment widely used in S. Korea. Therefore, a new data acquisition board working on Windows OS was designed and built. The board mainly consists of FPGA (Field Programmable Gate Array) and SoC (System on Chip) for TTL pulse readout, sorting measured data, and transferring data to a user interface. In conclusion, the tomographic system at lab-scale has shown considerable potential to detect a partial or gross defect of encapsulated assemblies in dry storage. Next steps of this study will be to 1) repeatedly carry out experiments to demonstrate scientific reliability and validity, and 2) numerically integrate signals with weight factors to enhance the image quality since the suggested system based on passive interrogation method requires longer measurement time. Finally, the system will apply to a commercial dry storage phased out soon in S. Korea. (authors)

07 ISOTOPE AND RADIATION SOURCES↗
DOE OSTI2021

Low-Temperature 2D/2D Ohmic Contacts in WSe 2 Field-Effect Transistors as a Platform for the 2D Metal–Insulator Transition

in this work, we report the fabrication of hexagonal-boron-nitride (hBN) encapsulated multiterminal WSe 2 Hall bars with 2D/2D low-temperature Ohmic contacts as a platform for investigating the two-dimensional (2D) metal-insulator transition. We demonstrate that the WSe 2 devices exhibit Ohmic behavior down to 0.25 K and at low enough excitation voltages to avoid current-heating effects. Additionally, the high-quality hBN-encapsulated WSe 2 devices in ideal Hall-bar geometry enable us to accurately determine the carrier density. Measurements of the temperature (T) and density (n s ) dependence of the conductivity σ(T, n s ) demonstrate scaling behavior consistent with a metalinsulator quantum phase transition driven by electron-electron interactions, but where disorder-induced local magnetic moments are also present. Our findings pave the way for further studies of the fundamental quantum mechanical properties of 2D transition metal dichalcogenides using the same contact engineering.

2D materials↗
NASA NTRS2011

Development of a 150-GHz MMIC Module Prototype for Large-Scale CMB Radiation

HEMT-based receiver arrays with excellent noise and scalability are already starting to be manufactured at 100 GHz, but the advances in technology should make it possible to develop receiver modules with even greater operation frequency up to 200 GHz. A prototype heterodyne amplifier module has been developed for operation from 140 to 170 GHz using monolithic millimeter-wave integrated circuit (MMIC) low-noise InP high electron mobility transistor (HEMT) amplifiers. The compact, scalable module is centered on the 150-GHz atmospheric window using components known to operate well at these frequencies. Arrays equipped with hundreds of these modules can be optimized for many different astrophysical measurement techniques, including spectroscopy and interferometry. This module is a heterodyne receiver module that is extremely compact, and makes use of 35-nm InP HEMT technology, and which has been shown to have excellent noise temperatures when cooled cryogenically to 30 K. This reduction in system noise over prior art has been demonstrated in commercial mixers (uncooled) at frequencies of 160-180 GHz. The module is expected to achieve a system noise temperature of 60 K when cooled. An MMIC amplifier module has been designed to demonstrate the feasibility of expanding heterodyne amplifier technology to the 140 to 170-GHz frequency range for astronomical observations. The miniaturization of many standard components and the refinement of RF interconnect technology have cleared the way to mass-production of heterodyne amplifier receivers, making it a feasible technology for many large-population arrays. This work furthers the recent research efforts in compact coherent receiver modules, including the development of the Q/U Imaging ExperimenT (QUIET) modules centered at 40 and 90 GHz, and the production of heterodyne module prototypes at 90 GHz.

Kangaslahti, Pekka P.↗
NASA NTRS2015

CarbAl Heat Transfer Material

The increasing use of power electronics, such as high-current semiconductor devices and modules, within space vehicles is driving the need to develop specialty thermal management materials in both the packaging of these discrete devices and the packaging of modules consisting of these device arrays. Developed by Applied Nanotech, Inc. (ANI), CarbAl heat transfer material is uniquely characterized by its low density, high thermal diffusivity, and high thermal conductivity. Its coefficient of thermal expansion (CTE) is similar to most power electronic materials, making it an effective base plate substrate for state-of-the-art silicon carbide (SiC) super junction transistors. The material currently is being used to optimize hybrid vehicle inverter packaging. Adapting CarbAl-based substrates to space applications was a major focus of the SBIR project work. In Phase I, ANI completed modeling and experimentation to validate its deployment in a space environment. Key parameters related to cryogenic temperature scaling of CTE, thermal conductivity, and mechanical strength. In Phase II, the company concentrated on improving heat sinks and thermally conductive circuit boards for power electronic applications.

Fink, Richard↗
NASA NTRS1995

Resonant Tunneling Analog-To-Digital Converter

As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.

Broekaert, T. P. E.↗
NASA NTRS2018

Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.

Neudeck, Philip G.↗
DOE OSTI2021

Electrochemical ion insertion from the atomic to the device scale

Electrochemical ion insertion involves coupled ion–electron transfer reactions, transport of guest species and redox of the host. The hosts are typically anisotropic solids with 2D conduction planes but can also be materials with 1D or isotropic transport pathways. These insertion compounds have traditionally been studied in the context of energy storage but also find extensive applications in electrocatalysis, optoelectronics and computing. Recent developments in operando, ultrafast and high-resolution characterization methods, as well as accurate theoretical simulation methods, have led to a renaissance in the understanding of ion-insertion compounds. In this Review, we present a unified framework for understanding insertion compounds across timescales and length scales ranging from atomic to device levels. Using graphite, transition metal dichalcogenides, layered oxides, oxyhydroxides and olivines as examples, we explore commonalities in these materials in terms of point defects, interfacial reactions and phase transformations. We illustrate similarities in the operating principles of various ion-insertion devices, ranging from batteries and electrocatalysts to electrochromics and thermal transistors, with the goal of unifying research across disciplinary boundaries.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Phase segregation mechanisms of small molecule-polymer blends unraveled by varying polymer chain architecture

As phase separation between the small-molecule semiconductor and the polymer binder is the key enabler of blend-based organic field-effect transistors (OFETs) fabricated by low-cost solution processing, it is crucial to understand the underlying phase separation mechanisms that determine the phase morphology, which significantly impacts device performance. Beyond the parameter space investigated in previous work, here we investigate the formation of blends by varying the branch architecture of the polymer binder and by shortening the solvent dry time using ultrasonic spray casting. The phase morphologies of the resulting blend films have been thoroughly characterized with a variety of techniques in three dimensions over multiple length scales, including AFM, energy-filtered transmission electron microscope, and neutron reflectivity, and have been correlated with electrical transport performance. From the results, we have inferred that the phase morphology is kinetically determined, limited by the inherent slow movement of polymer macromolecules. The kinetic picture, supported by molecular dynamics modeling, not only consistently explains our observations but also resolves inconsistencies in previous works. The achieved mechanistic understanding will guide further optimization of blend-based organic electronics, such as OFETs and organic photovoltaics.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. Further, the different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

36 MATERIALS SCIENCE↗
NASA NTRS1999

Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-(micron)meter MOSFET's with Epitaxial and (delta)-Doped Channels

A detailed three-dimensional (3-D) statistical 'atomistic' simulation study of fluctuation-resistant sub-0.1-(micron)meter MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-(micron)meter generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channel. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-(micron)meter devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta-doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-(micron)meter MOSFET's. Index Terms-Doping, fluctuations, MOSFET, semiconductor device simulation, silicon devices, threshold.

Asenov, Asen↗
DOE OSTI2022

Material aspects of giga-Hertz ZnO TFTs for wireless systems

Abstract Having enabled high-value application capabilities through mass production of flat-panel displays, X-ray imagers, and solar panels, Large-Area Electronics (LAE) holds potential to open new frontiers in wireless applications for the Internet of Things and 5G/6G, by enabling unprecedented spatial control and power efficiency through large size and flexible form factor of radiative apertures. However, this requires boosting operation frequencies from the traditional limits in the range of 10–100’s of mega-Hertz to multi giga-Hertz. In this paper, we discuss critical device metrics, to characterize zinc-oxide (ZnO) thin-film transistor (TFT) operation frequency for both active (for signal amplification) and passive components in LAE-based circuits and systems. We then describe the key structural and material approaches towards recently demonstrated LAE-based giga-Hertz wireless systems employing ZnO TFTs. Bringing LAE to the giga-Hertz regime provides a path towards flexible and meter-scale monolithic integrated wireless systems. Graphical abstract

Ma, Yue (ORCID:0000000186724090)↗
DOE OSTI2023

A Smart Silicon Carbide Power Module With Pulse Width Modulation Over Wi-Fi and Wireless Power Transfer-Enabled Gate Driver, Featuring Onboard State of Health Estimator and High-Voltage Scaling Capabilities

A wide range of utility applications require controllable switches with features such as high-voltage blocking and high-current carrying capacity, especially at high pulse width modulation (PWM) frequency. Low- and medium-voltage utility applications such as motor drives and flexible AC transmission systems as well as solid state transformers could also benefit from a low-cost high-voltage switching module. Wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) metal oxide semiconductor field effect transistors (MOSFETs) are considered to be the present and next-generation device choices, although they have limitations. For relatively high-voltage applications with demanding thermal management, SiC is still the only choice, and GaN dominates the low-voltage regime. This manuscript proposes a new half-bridge power MOSFET module that is suitable for conventional H-bridge of multilevel configurations used in high-voltage applications. Constructed from bare SiC dies, this half-bridge module takes advantage of (1) optimized MOSFET placement inside the module, (2) customized heat exchanger, manifold, and cooling, (3) integrated gate driver module with pulse width modulation (PWM) over wi-fi to eliminate the need for low-voltage signals, (4) wireless power transfer (WPT)-enabled gate driver and other ancillary circuits, (5) and the option to incorporate an onboard state-of-health (SOH) estimator module. The entire architecture has been designed and built at the National Renewable Energy Laboratory (NREL) in Golden, CO.

Ga2O3 devices↗
DOE OSTI2024

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

Abstract This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and$$\text {Hf}_{0.5}\text {Zr}_{0.5}\text {O}_2$$ Hf 0.5 Zr 0.5 O 2 (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

Science & Technology - Other Topics↗
NASA NTRS1987

The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

Hsu, I. S.↗
NASA NTRS1994

Nonvolatile programmable neural network synaptic array

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Tawel, Raoul↗
NASA NTRS2016

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

high temperature↗