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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,585 records · Page 88
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Ground-referenced single-ended system-on-package

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.

Dally, William J.↗
DOE OSTI2019

System and method for instantaneous power decomposition and estimation

A system disaggregates and estimates power consumption of electric loads powered by a single electrical outlet. The system includes a processor having a routine; a current sensor cooperating with the processor to measure samples for one line cycle of an aggregated current waveform for the electric loads powered by the single electrical outlet; and a voltage sensor cooperating with the processor to measure samples for the one line cycle of a voltage waveform for the electric loads powered by the single electrical outlet. The processor routine transfers the measured samples for the one line cycle of the aggregated current waveform and the voltage waveform into an aggregated voltage-current trajectory for the single electrical outlet, and provides an instantaneous decomposition of power consumption for a plurality of different categories of the electric loads from the aggregated voltage-current trajectory for the one line cycle.

Yang, Yi↗
DOE OSTI2019

Network-aware cache coherence protocol enhancement

A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.

Roberts, David A.↗
DOE OSTI2020

Methods and apparatus to modify a binary file for scalable dependency loading on distributed computing systems

Methods and apparatus to modify a binary file for scalable loading on distributed computing systems are disclosed. An example method to modify a binary file for scalable loading on a distributed computing system includes identifying, by executing an instruction with a processor, in the binary file a file name for a shared file, determining, by executing an instruction with the processor, whether the shared file can be loaded based on a path name specified in the binary file, and, responsive to a determination that the shared file can be loaded, generating, by executing an instruction with the processor, an identifier that can be used to access a local file scalably copied from a global file system, and modifying, by executing an instruction with the processor, the binary file by replacing, in the binary file, the file name with the generated identifier.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Redirecting data to improve page locality in a scalable data fabric

A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

System and method to characterize and identify operating modes of electric loads

A system characterizes and identifies one of a plurality of different operating modes of a number of electric loads. The system includes a processor; a voltage sensor providing a voltage signal for one of the electric loads to the processor; a current sensor providing a current signal for the one electric load to the processor; and a routine executed by the processor and structured to characterize the different operating modes using steady state and voltage-current trajectory features determined from the voltage and current signals, and to identify a particular one of the different operating modes based on a plurality of operating mode membership functions of the steady state and voltage-current trajectory features.

Yang, Yi↗
DOE OSTI2021

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Jayasena, Nuwan S.↗
DOE OSTI2022

Systems and methods for plane-wave and fan-beam ultrasound-waveform tomography

A method for plane-wave or fan-beam ultrasound tomography includes: controlling, by a processor, a multi-channel ultrasound array controller to control a linear ultrasound transducer array to emit plane-wave or fan-beam ultrasound into a biological tissue, the linear ultrasound transducer array including a plurality of transducers; receiving, by the processor, plane-wave or fan-beam ultrasound waveform data from the transducers, the plane-wave or fan-beam ultrasound waveform data including reflections of the plane-wave or fan-beam ultrasound from the biological tissue; computing, by the processor, a synthetic ultrasound-waveform inversion from the received plane-wave or fan-beam ultrasound waveform data; and computing, by the processor, an image of the biological tissue from the synthetic ultrasound-waveform inversion.

Huang, Lianjie↗
DOE OSTI2023

Last-level collective hardware prefetching

A last-level collective hardware prefetcher (LLCHP) is described. The LLCHP is to detect a first off-chip memory access request by a first processor core of a plurality of processor cores. The LLCHP is further to determine, based on the first off-chip memory access request, that first data associated with the first off-chip memory access request is associated with second data of a second processor core of the plurality of processor cores. The LLCHP is further to prefetch the first data and the second data based on the determination.

Michelogiannakis, Georgios↗
DOE OSTI2023

System and method for predicting the presence of rare earth elements

A system for predicting rare earth elements (REEs) in a feedstock sample includes a measurement instrument that records a measurement for a sample, a processor communicatively coupled to the measuring instrument, and a memory communicatively coupled to the processor and containing machine readable instructions that, when executed by the processor, cause the processor to correlate the measurement series using a model; and predict a presence of one or more rare earth element based at least in part on the correlation. A method for predicting rare earth elements includes measuring feedstock samples via XRF or PGNAA, to generate a measurements of elements of interest with a lower atomic weight than REEs; correlating the measurements with a model; and predicting a presence of one or more rare earth elements based at least in part on the correlation.

Fuka, Matthew↗
DOE OSTI2017

An automatic input/output test experience of FPGA-based logic controller with I/O stimulator - 282

This paper describes an automatic testing approach instead of a traditional manual test for an FPGA-based Logic Controller (FLC). It mainly describes an automatic testing of FLC using an I/O stimulator with the initiated manual action. The FLC was developed by Doosan Heavy Industry and KAERI in S. Korea. We also developed a test-bed like I/O stimulator for a burning test based on the operational scenario. Signal sources from the I/O stimulator contain an analog input, an analog output, a digital input and a digital output, a programmable power supply, an RS232C serial interface, and a dual port Ethernet interface. LabVIEW Programming was used for the automatic testing. The FLC consists of a general processor module (FPM-01), a complex processor module (FPM-02), analog input modules (FAI-01), analog output modules (FAO-01), digital input modules (FDI-01), digital output modules (FDO-01), a data link module (FDL-01), and a network module (FNW-01). Among these, in this paper, automatic digital I/O testing and automatic analog I/O testing are described. In addition, for the accuracy of the automatic testing, two graphic recorders are used. One is the output results of general processor based testing, and the other is the output results of complex processor based testing. These are different company products. Redundancy recording was found in the test results. The test results were synchronized internally with the existing I/O stimulator and externally with two graphic recorders. Calibrations of all of the equipment were made before the system testing. Before the testing started, a test plan and the test procedure were set up in advance, and we performed test scenario-based automatic functional testing for the FLC as the qualification process. It can be several executed depending on the scenario and conditional parameters of the test. For validation of the accuracy and reliability in our automated test, manual testing was also performed. Manual tests were conducted in two ways. The first one was a manual test using Fluke 754 and Fluke 715. The other one was using embedded manual features of the I/O stimulator. By performing the automatic input and output testing using the I/O stimulator, the time and expense of FLC testing can be reduced significantly compared with a conventional manual test. We rechecked the automatic test results using Fluke754 manually. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Chemical detection system with at least one electronic nose

A system for predicting one or more analytes based on outputs from thin film gas sensors is provided. The system may comprise an electronic nose (e-nose). The e-nose may comprise the gas sensors and a first processor. The system may further comprise a second processor. The second processor may be configured to receive the output from each of the gas sensors, evaluate a prediction accuracy using an evaluation parameter of each of a plurality of models which are trained and tested and select a model from among the plurality of models to deploy based on a comparison of the evaluation parameter for each of the plurality of models and use the same. The second processor may also receive, an output of each of the gas sensors caused by unknown one or more analytes; and predict, using the deployed model, the one or more analytes that causes the output.

Ivanov, Ilia N.↗
DOE OSTI2015

A Framework to Analyze the Performance of Load Balancing Schemes for Ensembles of Stochastic Simulations

Ensembles of simulations are employed to estimate the statistics of possible future states of a system, and are widely used in important applications such as climate change and biological modeling. Ensembles of runs can naturally be executed in parallel. However, when the CPU times of individual simulations vary considerably, a simple strategy of assigning an equal number of tasks per processor can lead to serious work imbalances and low parallel efficiency. This paper presents a new probabilistic framework to analyze the performance of dynamic load balancing algorithms for ensembles of simulations where many tasks are mapped onto each processor, and where the individual compute times vary considerably among tasks. Four load balancing strategies are discussed: most-dividing, all-redistribution, random-polling, and neighbor-redistribution. Simulation results with a stochastic budding yeast cell cycle model are consistent with the theoretical analysis. It is especially significant that there is a provable global decrease in load imbalance for the local rebalancing algorithms due to scalability concerns for the global rebalancing algorithms. The overall simulation time is reduced by up to 25 %, and the total processor idle time by 85 %.

ALGORITHMS↗
NASA NTRS1994

Remote Objects Message Exchange (ROME)

The performance of a single program running on a single processor is limited by the character of the processor. Moreover, the cost and difficulty of developing and sustaining programs tend to increase as their size and complexity increase. Clearly there ought to be some advantage in partitioning powerful application software in relatively small and simple components that can run in parallel on multiple processors; the software should run faster and it should be cheaper and easier to deploy. Remote Objects Message Exchange (ROME) is an attempt to provide a single relatively simple, universally available abstraction for data communication among C++ objects. It aims to enable the C++ application developer to specify objects' interactions with other objects wholly in terms of the application domain, without concern for details of interprocess communication. Every ROME-compliant object is conceptually a network peer of every other, as if each one were (for example) a separate UNIX process.

processors application software data communication↗
NASA NTRS2018

High-Performance Spaceflight Computing (HPSC) Project Overview

The High Performance Spaceflight Computing (HPSC) multi-core processor Chiplet will provide a nearly two orders-of-magnitude improvement above the current state of the art for spaceflight processors, while also providing an unprecedented flexibility to tailor performance, power consumption, and fault tolerance to meet widely varying mission needs. These advancements will provide game changing improvements in computing performance, power efficiency, and flexibility, which will significantly improve the onboard processing capabilities of future NASA and Air Force space missions. HPSC is funded by NASA's Space Technology Mission Directorate (STMD), Science Mission Directorate (SMD), and the United States Air Force. The HPSC project is managed by Jet Propulsion Laboratory, and the HPSC contract is managed by NASA Goddard Space Flight Center (GSFC). Within the HPSC project, Boeing is under contract to NASA to develop prototype Chiplets, system software, and evaluation boards. As another development within the project, NASA Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL) are developing middleware that will simplify application development for HPSC-based onboard processors.

multi-core processor↗
DOE OSTI2022

Enabling power measurement and control on Astra: The first petascale Arm supercomputer

Astra, deployed in 2018, was the first petascale supercomputer to utilize processors based on the ARM instruction set. The system was also the first under Sandia's Vanguard program which seeks to provide an evaluation vehicle for novel technologies that with refinement could be utilized in demanding, large-scale HPC environments. In addition to ARM, several other important first-of-a-kind developments were used in the machine, including new approaches to cooling the datacenter and machine. Here we document our experiences building a power measurement and control infrastructure for Astra. While this is often beyond the control of users today, the accurate measurement, cataloging, and evaluation of power, as our experiences show, is critical to the successful deployment of a large-scale platform. While such systems exist in part for other architectures, Astra required new development to support the novel Marvell ThunderX2 processor used in compute nodes. In addition to documenting the measurement of power during system bring up and for subsequent on-going routine use, we present results associated with controlling the power usage of the processor, an area which is becoming of progressively greater interest as data centers and supercomputing sites look to improve compute/energy efficiency and find additional sources for full system optimization.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2016

Data Movement in Data-Intensive High Performance Computing.

The cost of executing a floating point operation has been decreasing for decades at a much higher rate than that of moving data. Bandwidth and latency, two key metrics that determine the cost of moving data, have degraded significantly relative to processor cycle time and execution rate. Despite the limitation of sub-micron processor technology and the end of Dennard scaling, this trend will continue in the short-term making data movement a performance-limiting factor and an energy/power efficiency concern. Even more so in the context of large-scale and data-intensive systems and workloads. This chapter gives an overview of the aspects of moving data across a system, from the storage system to the computing system down to the node and processor level, with case study and contributions from researchers at the San Diego Supercomputer Center, the Oak Ridge National Laboratory, the Pacific Northwest National Laboratory, and the University of Delaware.

Data Movement↗
DOE OSTI2025

Mesh-based super-resolution of fluid flows with multiscale graph neural networks

A graph neural network (GNN) approach is introduced in this work which enables mesh-based three-dimensional super-resolution of fluid flows. In this framework, the GNN is designed to operate not on the full mesh-based field at once, but on localized meshes of elements (or cells) directly. To facilitate mesh-based GNN representations in a manner similar to spectral (or finite) element discretizations, a baseline GNN layer (termed a message passing layer, which updates local node properties) is modified to account for synchronization of coincident graph nodes, rendering compatibility with commonly used element-based mesh connectivities. Furthermore, the architecture is multiscale in nature, and is comprised of a combination of coarse-scale and fine-scale message passing layer sequences (termed processors) separated by a graph unpooling layer. The coarse-scale processor embeds a query element (alongside a set number of neighboring coarse elements) into a single latent graph representation using coarse-scale synchronized message passing over the element neighborhood, and the fine-scale processor leverages additional message passing operations on this latent graph to correct for interpolation errors. Demonstration studies are performed using hexahedral mesh-based data from Taylor–Green Vortex and backward-facing step flow simulations at Reynolds numbers of 1600 and 3200. Through analysis of both global and local errors, the results ultimately show how the GNN is able to produce accurate super-resolved fields compared to targets in both coarse-scale and multiscale model configurations. Reconstruction errors for fixed architectures were found to increase in proportion to the Reynolds number. Geometry extrapolation studies on a separate cavity flow configuration show promising cross-mesh capabilities of the super-resolution strategy.

Backward-facing step↗