Design of a Multiple-Output Voltage Generator PCB for a Comprehensive Verification of the PSEC6, a 1-ps Resolution Mixed-Signal ASIC
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Rico Aniles, Hector Daniel [North Central Coll.]↗
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SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators
Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension
Minutoli, Marco↗
A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg
Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.
radiation hardened by design↗
Development of a large active area beam telescope based on the SiD microstrip sensor
A beam telescope as one of the most important and often requested test beam equipment provides particle tracking to test beam users. At the DESY II test beam facility, a new beam telescope called Lycorisbased on a microstrip sensor has been designed to address the user demands for momentum measurement in a 1 T solenoid magnet or large area tracking with limited space (3.5 cm between the potential user device and the magnet inner wall). Lycorisis designed to provide a high-precision resolution of at least ~10 µm along the bending direction, and a large active area of 10x10 cm 2 to cover at least 90% of the beam particles at energies of 1-6 GeV. The microstrip sensor was originally designed for the Silicon Detector (SiD) at the International Linear Collider (ILC), which adopted a hybrid-less design, i.e. a second metallization layer is used to route signals from strips to the bump-bonded ASIC, and from the ASIC to a wire-bond pad to the outside. This hybrid-less arrangement eliminates the need for a complex hybrid design, and its functioning is first-time tested in this project. The performance of the sensor modules was firstly tested in the lab then at the DESY II test beam facility in August/September 2018, and the results will be presented here. In addition, a summary will be given at the end with an overview of the ongoing test beam campaign of the Lycorisprototype in February 2019.
47 OTHER INSTRUMENTATION↗
Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus
The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.
flight computers↗
Data Concentrator
Orbital Research, Inc., developed, built, and tested three high-temperature components for use in the design of a data concentrator module in distributed turbine engine control. The concentrator receives analog and digital signals related to turbine engine control and communicates with a full authority digital engine control (FADEC) or high-level command processor. This data concentrator follows the Distributed Engine Controls Working Group (DECWG) roadmap for turbine engine distributed controls communication development that operates at temperatures at least up to 225 C. In Phase I, Orbital Research developed detailed specifications for each component needed for the system and defined the total system specifications. This entailed a combination of system design, compiling existing component specifications, laboratory testing, and simulation. The results showed the feasibility of the data concentrator. Phase II of this project focused on three key objectives. The first objective was to update the data concentrator design modifications from DECWG and prime contractors. Secondly, the project defined requirements for the three new high-temperature, application-specific integrated circuits (ASICs): one-time programmable (OTP), transient voltage suppression (TVS), and 3.3V. Finally, the project validated each design by testing over temperature and under load.
Willett, Mike↗
Remote Memory Access Protocol Target Node Intellectual Property
The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.
Haddad, Omar↗
High performance VLSI telemetry data systems
NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.
Chesney, J.↗
Characterization of 128 × 128 MM-PAD-2.1 ASIC: a fast framing hard x-ray detector with high dynamic range
Here, we characterize a new x-ray Mixed-Mode Pixel Array Detector (MM-PAD-2.1) Application Specific Integrated Circuit (ASIC). Using an integrating pixel front-end with dynamic charge removal architecture, the MM-PAD-2.1 ASIC extends the maximum measurable x-ray signal (in 20 keV photon units) to > 10 7 x-rays/pixel/frame while maintaining a low read noise across the full dynamic range, all while imaging continuously at a frame rate of up to 10 kHz. The in-pixel dynamic charge removal mechanism prevents saturation of the input amplifier and proceeds in parallel with signal integration to achieve deadtime-less measurements with incident x-ray rates of > 10 10 x-rays/pixel/s. The ASIC format consists of 128 × 128 square pixels each 150 μm on a side and is designed to be 3-side buttable so large arrays can be effectively tiled. Here we use both laboratory x-ray sources and the Cornell High Energy Synchrotron Source (CHESS) to characterize two single ASIC prototype detectors for both low (single x-ray) and high incident flux detection. In the first detector the ASIC was solder bump-bonded to a 500 μm thick Si sensor for efficient detection of x-rays below 20 keV, whereas the second detector used a 750 μm thick CdTe sensor for x-rays above ~20 keV.
36 MATERIALS SCIENCE↗
Programmable digital modem
The design of the Programmable Digital Modem (PDM) is outlined. The PDM will be capable of operating with numerous modulation techniques including: 2-, 4-, 8- and 16-ary phase shift keying (PSK), minimum shift keying (MSK), and 16-ary quadrature amplitude modulation (QAM), with spectral occupancy from 1.2x to 2x the data symbol rate. It will also be programmable for transmission rates ranging from 2.34 to 300 Mbit/s, where the maximum symbol rate is 75 Msymbol/s. Furthermore, these parameters will be executable in independent burst, dependent burst, or continuous mode. In dependent burst mode the carrier and clock oscillator sources are common from burst to burst. To achieve as broad a set of requirements as these, it is clear that the essential signal processing must be digital. In addition, to avoid hardware changes when the operational parameters are changed, a fixed interface to an analog intermediate frequency (IF) is necessary for transmission; and, common system level architectures are necessary for the modulator and demodulator. Lastly, to minimize size and power, as much of the design as possible will be implemented with application specific integrated circuit (ASIC) chips.
Poklemba, John J.↗
NASA/BAE SYSTEMS SpaceWire Effort
This paper discusses the state of the NASA and BAE SYSTEMS developments of SpaceWire. NASA has developed intellectual property that implements SpaceWire in Register Transfer Level (RTL) VHDL for a SpaceWire link and router. This design has been extensively verified using directed tests from the SpaceWire Standard and design specification, as well as being randomly tested to flush out hard to find bugs in the code. The high level features of the design will be discussed, including the support for multiple time code masters, which will be useful for the James Webb Space Telescope electrical architecture. This design is now ready to be targeted to FPGA's and ASICs. Target utilization and performance information will be presented for Spaceflight worthy FPGA's and a discussion of the ASIC implementations will be addressed. In particular, the BAE SYSTEMS ASIC will be highlighted which will be implemented on their .25micron rad-hard line. The chip will implement a 4-port router with the ability to tie chips together to make larger routers without external glue logic. This part will have integrated LVDS drivers/receivers, include a PLL and include skew control logic. It will be targeted to run at greater than 300 MHz and include the implementation for the proposed SpaceWire transport layer. The need to provide a reliable transport mechanism for SpaceWire has been identified by both NASA And ESA, who are attempting to define a transport layer standard that utilizes a low overhead, low latency connection oriented approach that works end-to-end. This layer needs to be implemented in hardware to prevent bottlenecks.
Rakow, Glenn Parker↗
NASA/BAE Systems SpaceWire Efforts
This paper discusses the state of the NASA and BAE SYSTEMS developments using Spacewire. NASA has developed intellectual property that implements Spacewire in Register Transfer Level VHDL for a Spacewire link and router. This design has been extensively verified using directed tests from the Spacewire Standard and design specification, as well as being randomly tested to flush out hard to find bugs in the code. The high level features of the design will be discussed, including the support for multiple time code masters, which will be useful for the James Webb Space Telescope electrical architecture. This design is now ready to be targeted to FPGA's and ASICs. Target utilization and performance information will be presented for some spaceflight qualified FPGA's and a discussion of the ASIC implementations will be addressed. In particular, the BAE SYSTEMS ASIC will be highlighted which will be implemented in their 0.25 micron rad-hard line. The chip will implement a 4-port router with the ability to tie chips together to make larger routers without external glue logic. This part will have integrated LVDS driver/receivers, include a PLL and include skew control logic. It will be targeted to run at greater than 300 MHz and include the implementation for the proposed Spacewire transport layer. The need to provide a reliable transport mechanism for Spacewire has been identified by both NASA and ESA, who are attempting to define a transport layer standard that utilizes a low overhead, low latency connection oriented approach. The Transport layer needs to be implemented in hardware-to prevent bottlenecks.
Rakow, Glenn Parker↗
Low-Power Architectures for Large Radio Astronomy Correlators
The architecture of a cross-correlator for a synthesis radio telescope with N greater than 1000 antennas is studied with the objective of minimizing power consumption. It is found that the optimum architecture minimizes memory operations, and this implies preference for a matrix structure over a pipeline structure and avoiding the use of memory banks as accumulation registers when sharing multiply-accumulators among baselines. A straw-man design for N = 2000 and bandwidth of 1 GHz, based on ASICs fabricated in a 90 nm CMOS process, is presented. The cross-correlator proper (excluding per-antenna processing) is estimated to consume less than 35 kW.
signal processing↗
Design, construction, and test of the Gas Pixel Detectors for the IXPE mission
Due to be launched in late 2021, the Imaging X-ray Polarimetry Explorer (IXPE) is a NASA Small Explorer mission designed to perform polarization measurements in the 2–8 keV band, complemented with imaging, spectroscopy and timing capabilities. At the heart of the focal plane is a set of three polarization-sensitive Gas Pixel Detectors (GPD), each based on a custom ASIC acting as a charge-collecting anode. In this paper we shall review the design, manufacturing, and test of the IXPE focal-plane detectors, with particular emphasis on the connection between the science drivers, the performance metrics and the operational aspects. We shall present a thorough characterization of the GPDs in terms of effective noise, trigger efficiency, dead time, uniformity of response, and spectral and polarimetric performance. In addition, we shall discuss in detail a number of instrumental effects that are relevant for high-level science analysis—particularly as far as the response to unpolarized radiation and the stability in time are concerned.
79 ASTRONOMY AND ASTROPHYSICS↗
Design and construction of the CMS Outer Tracker for the phase-2 upgrade
The High-Luminosity LHC (HL-LHC) is expected to deliver an integrated luminosity of 3000–4000 fb −1 over 10 years of operation with the peak instantaneous luminosity reaching about 5–7.5 × 1 0 34 cm −2 s −1 . During Long Shutdown 3, several components of the CMS detector will undergo major improvements, called Phase-2 upgrades, to be able to operate in the challenging environment of the HL-LHC. The current CMS tracker will be replaced. The Phase-2 Outer Tracker (OT) will have increased radiation tolerance, higher granularity, and the capability to handle higher data rates. Moreover, the OT will provide tracking information to the Level-1 trigger for the first time at a hadron collider, allowing trigger rates to be kept at a sustainable level without sacrificing physics potential. For this, the OT will be made of modules with two closely-spaced silicon sensors read out by front-end ASICs that can correlate hits in the two sensors to create short track segments, used in the Level-1 track finder. The modules come in two flavors: strip-strip and pixel-strip, containing different sensor configurations and multiple ASICs. This contribution presents the Phase-2 OT, the finalization of the OT module design, and the quality assurance and control procedures used to ensure that the modules fulfill both the specifications from the assembly steps as well as the proper communication among the ASICs.
Zoi, Irene [Fermilab] (ORCID:0000000257389446)↗
Digital circuits using universal logic gates
According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.
Whitaker, Sterling R.↗
The Magnetospheric Multiscale Magnetometers
The success of the Magnetospheric Multiscale mission depends on the accurate measurement of the magnetic field on all four spacecraft. To ensure this success, two independently designed and built fluxgate magnetometers were developed, avoiding single-point failures. The magnetometers were dubbed the digital fluxgate (DFG), which uses an ASIC implementation and was supplied by the Space Research Institute of the Austrian Academy of Sciences and the analogue magnetometer (AFG) with a more traditional circuit board design supplied by the University of California, Los Angeles. A stringent magnetic cleanliness program was executed under the supervision of the Johns Hopkins University,s Applied Physics Laboratory. To achieve mission objectives, the calibration determined on the ground will be refined in space to ensure all eight magnetometers are precisely inter-calibrated. Near real-time data plays a key role in the transmission of high-resolution observations stored onboard so rapid processing of the low-resolution data is required. This article describes these instruments, the magnetic cleanliness program, and the instrument pre-launch calibrations, the planned in-flight calibration program, and the information flow that provides the data on the rapid time scale needed for mission success.
Magnetosphere↗
A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade
We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity correction, respectively. The TDC block consumes 97 W at the hit occupancy of 1%. Over a temperature range from 23 C to 78 C and a power supply voltage range from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation-tolerance specifications.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗