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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Optimized low-depth quantum circuits for molecular electronic structure using a separable-pair approximation

We present a classically tractable model that leads to optimized low-depth quantum circuits leveraging separable-pair approximations. The obtained circuits are well suited as a baseline circuit for emerging quantum hardware and can, in the long term, provide significantly improved initial states for quantum algorithms. The associated wave functions can be represented with linear memory requirement, which allows classical optimization of the circuits and naturally defines a minimum benchmark for quantum algorithms. In this work we employ directly determined pair-natural orbitals within a basis-set-free approach. This leads to accurate representation of the one- and many-body parts for weakly correlated systems and we explicitly illustrate how the model can be integrated into other quantum algorithms for stronger correlated systems.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2024

Benchmarking characterization methods for noisy quantum circuits

Effective methods for characterizing the noise in quantum computing devices are essential for programming and debugging circuit performance. Existing approaches vary in the information obtained as well as the amount of quantum and classical resources required, with more information generally requiring more resources. Here we benchmark the characterization methods of gate set tomography, Pauli channel noise reconstruction, and empirical direct characterization for developing models that describe noisy quantum circuit performance on a 27-qubit superconducting transmon device. We evaluate these models by comparing the accuracy of noisy circuit simulations with the corresponding experimental observations. Here, we find that the agreement of noise model to experiment does not correlate with the information gained by characterization and that the underlying circuit strongly influences the best choice of characterization approach. Empirical direct characterization scales best of the methods we tested and produced the most accurate characterizations across our benchmarks.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2020

ADMX SLIC: Results from a Superconducting $\textit{LC}$ Circuit Investigating Cold Axions

Axions are a promising cold dark matter candidate. Haloscopes, which use the conversion of axions to photons in the presence of a magnetic field to detect axions, are the basis of microwave cavity searches such as the Axion Dark Matter eXperiment (ADMX). To search for lighter, low frequency axions in the sub-2 × 10 –7 eV (50 MHz) range, a tunable lumped-element $\textit{LC}$ circuit has been proposed. For the first time, through ADMX SLIC (Superconducting $\textit{LC}$ Circuit Investigating Cold Axions), a resonant $\textit{LC}$ circuit was used to probe this region of axion mass-coupling space. The detector used a superconducting $\textit{LC}$ circuit with piezoelectric driven capacitive tuning. The axion mass and corresponding frequency ranges 1.7498–1.7519 × 10 –7 eV (42.31–42.36 MHz), 1.7734–1.7738 × 10 –7 eV (42.88–42.89 MHz), and 1.8007–1.8015 × 10 –7 eV (43.54–43.56 MHz) were covered at magnetic fields of 4.5 T, 5.0 T, and 7.0 T, respectively. Exclusion results from the search data, for coupling below 10 –12 GeV –1 , are presented.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Mitigating Depolarizing Noise on Quantum Computers with Noise-Estimation Circuits

A significant problem for current quantum computers is noise. While there are many distinct noise channels, the depolarizing noise model often appropriately describes average noise for large circuits involving many qubits and gates. We present a method to mitigate the depolarizing noise by first estimating its rate with a noise-estimation circuit and then correcting the output of the target circuit using the estimated rate. The method is experimentally validated on the simulation of the Heisenberg model. We find that our approach in combination with readout-error correction, randomized compiling, and zero-noise extrapolation produces results close to exact results even for circuits containing hundreds of CNOT gates.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Acceptor-Induced Bulk Dielectric Loss in Superconducting Circuits on Silicon

The performance of superconducting quantum circuits is primarily limited by dielectric loss due to interactions with two-level systems (TLSs). State-of-the-art circuits with engineered material interfaces are approaching a limit where dielectric loss from bulk substrates plays an important role. However, a microscopic understanding of dielectric loss in crystalline substrates is still lacking. In this work, we show that boron acceptors in silicon constitute a TLS bath that leads to an energy dissipation channel for superconducting circuits. We discuss how the electronic structure of boron acceptors leads to an effective TLS response in silicon. We sweep the boron concentration in silicon and demonstrate the bulk dielectric loss limit from boron acceptors. We show that boron-induced dielectric loss can be reduced in a magnetic field due to the spin-orbit structure of boron. This work provides the first detailed microscopic description of a TLS bath for superconducting circuits and demonstrates the need for ultrahigh-purity substrates for next-generation superconducting quantum processors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

A Fast-Response High-Accuracy Overvoltage Protection Circuit for Soft-Switching Current-Source Converters

Although voltage-source converters (VSCs) have been a focus of research for decades and are widely applied in numerous applications, they face great challenges in short-circuit failures, high dv/dt and electromagnetic interference (EMI), especially using wide bandgap devices. Instead, current-source converters (CSCs) are attracting increasing attention in recent years owing to their friendliness to short-circuit faults, improved EMI, etc. For CSCs, overvoltage is the most catastrophic failure since the semiconductor devices can hardly withstand an overvoltage for a short pulse. In this paper, a fast-response high-accuracy overvoltage protection (OVP) circuit is proposed to protect CSCs from overvoltage damage. It also features a small form factor, good noise-immunity, friendly retrofit capability, and no need for active switches. In this paper, the operating principle and design guideline of the proposed OVP circuit is introduced. Its effectiveness is validated in soft-switching solid-state transformer (S4T) at 500 V. In experiments, the voltage detection error of less than 5% and a propagation delay of fewer than 400 ns have been achieved.

30 DIRECT ENERGY CONVERSION↗
DOE OSTI2024

Grid Forming Inverter With Increased Short-Circuit Contribution to Address Inverter-Based Microgrid Protection Challenges

Substantial differences in fault levels between grid-tied and islanded modes is one of the primary challenges of microgrid protection. During grid-tied mode, the bulk grid provides significant short-circuit, while during islanded operation the short-circuit magnitude is small due to inverter-based resources limiting their current output close to nominal ratings. Consequently, conventional distribution protection strategies based on overcurrent cannot reliably protect microgrids when operating in islanded mode. Fuses and circuit breakers are particularly affected because of their inverse characteristics. Presently, the absence of affordable solutions for protecting microgrids in islanded mode leads to microgrids shutting down during electrical faults. The contribution of this article is two-fold. The first innovation proposes specific hardware modifications to grid-forming inverters to increase their short-circuit current during electrical faults. The second innovation introduces a novel control strategy designed to preserve control stability margins even when the grid-filter saturates, ensuring sinusoidal output currents under normal and fault conditions. Through experimental results, the inverter with the proposed modifications can provide more than three-times its nominal current during electrical faults. For the prototype testbed, this was sufficient to enable the use of traditional legacy overcurrent protection, achieving the fuse-to-relay and relay-to-relay minimum coordination time for the line-to-ground, line-to-line to ground, and three-phase electrical faults.

42 ENGINEERING↗
DOE OSTI2023

Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine Learning

Here we propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of ~ 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2023

Quantum Noise Mitigation: Introducing the Robust Quantum Circuit Scheduler for Enhanced Fidelity and Throughput

Undoubtedly, quantum computing offers valuable acceleration for solving intricate problems. One of the primary hurdles lies in executing large-scale quantum applications on backend machines. Qubit noise, among other factors, dramatically influences the execution process. Implementing effective scheduling techniques for quantum circuits is crucial for practical quantum computing and preventing excessive waiting times. The quantum realm is distinct from classical computing in terms of optimization, performance, utilization, and waiting periods. Consequently, the parameters and components of quantum circuit scheduling diverge from those of classical computing. This paper presents Quantum Noise Mitigation: Introducing the Robust Quantum Circuit Scheduler for Enhanced Fidelity and Throughput, a straightforward yet effective scheduling framework and policy that enhances noise resilience, throughput, and the fidelity of quantum circuits. Drawing inspiration from classical methods, our scheduling approach incorporates additional constraints tailored for quantum logic. The outcome demonstrates a substantial improvement in fidelity and resource management, which is vital for real-world quantum applications.

Baheri, Betis↗
DOE OSTI2023

Temperature-Dependent Sheet and Contact Resistivity Measurements on Ag and Ag-Ni Circuit Pastes

The metal circuits and brazes used in electronic, energy conversion, and/or energy storage devices often have difficulty wetting and adhering to ceramic and/or ceramic-passivated metal substrates. Here, a novel Particle Interlayer Directed Wetting and Spreading (PIDWAS) technique is demonstrated that utilizes screen printing, the low wetting angle of silver on nickel, and the high work of adhesion between nickel and various ceramics to produce well-adhered, self-assembled silver patterns on ceramic and/or stainless-steel substrates not normally wet by silver. The resulting Ag-Ni circuits have higher sapphire adhesion strengths (up to 30 MPa on sapphire), higher densities (>97% on sapphire), and similar high-temperature electronic resistivities to those made using commercially-available Heraeus C8710 or DAD-87 silver circuit pastes. Similarly, Ag-Ni brazes between a variety of ceramic and/or stainless-steel substrates have better microstructural stability with rapid thermal cycling, reduction-oxidation cycling, and dual atmosphere isothermal aging than conventional Ag-CuO brazes. In addition, the residual Ni in these Ag-Ni circuits and brazes can be used to chemically getter surface segregated Al, ensuring low contact resistances on a variety of chromia- and/or alumina-passivated stainless steels. Reference: [1] Hu G, Zhou Q, Bhatlawande A, Park J, Termuhlen R, Ma Y, Bieler TR, Yu HC, Qi Y, Hogan T & Nicholas JD. Patterned Nickel Interlayers for Enhanced Silver Wetting, Spreading and Adhesion on Ceramic Substrates. Scripta Materialia, 2021; 196, 113767. 10.1016/j.scriptamat.2021.113767 [2] Park J, Phongpreecha T, Nicholas JD & Qi Y. Enhanced Liquid Metal Wetting on Oxide Surfaces via Patterned Particles. Acta Materialia, 2020; 199, 551-560. 10.1016/j.actamat.2020.08.037

Bhatlawande, Aishwarya↗
DOE OSTI2024

Atomic-level mechanisms of short-circuit diffusion in materials

This paper reviews the recent progress in understanding the atomic mechanisms of short-circuit diffusion along materials interfaces, such as grain and interphase boundaries, as well as lattice and interfacial dislocations/disconnections. Recent atomistic computer simulations have shown that short-circuit diffusion is dominated by collective atomic rearrangements in the form of strings and rings of mobile atoms. The process is dynamically heterogeneous in space and time and has many features in common with atomic dynamics in supercooled glass-forming liquids. We discuss examples of grain boundary, interphase boundary, and dislocation diffusion in metals and alloys, including the solute effect on the diffusion rates and mechanisms. Interphase boundaries are exemplified by Al–Si interfaces with diverse orientation relationships and atomic structures. The hierarchy of short-circuit diffusion paths in materials is reviewed by comparing the rates of grain boundary, interphase boundary, and dislocation diffusion. Future directions in the field of short-circuit diffusion in defect core regions are discussed.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Prediction of Circuit Response to an Electromagnetic Environment (ASC IC FY2020 Milestone 7179)

This report covers the work performed in support of the ASC Integrated Codes FY20 Milestone 7179. For the Milestone, Sandia's Xyce analog circuit simulator was enhanced to enable a loose coupling to Sandia's EIGER electromagnetic (EM) simulation tool. A device was added to Xyce that takes as its input network parameters (representing the impedance response) and short-circuit current induced in a wire or other element, as calculated by an EM simulator such as EIGER. Simulations were performed in EIGER and in Xyce (using Harmonic Balance analysis) for a variety of linear and nonlinear circuit problems, including various op amp circuits. Results of those simulations are presented and future work is also discussed.

42 ENGINEERING↗
DOE OSTI2024

Building spatial symmetries into parameterized quantum circuits for faster training

Practical success of quantum learning models hinges on having a suitable structure for the parameterized quantum circuit. Such structure is defined both by the types of gates employed and by the correlations of their parameters. While much research has been devoted to devising adequate gate-sets, typically respecting some symmetries of the problem, very little is known about how their parameters should be structured. In this work, we show that an ideal parameter structure naturally emerges when carefully considering spatial symmetries (i.e. the symmetries that are permutations of parts of the system under study). Namely, we consider the automorphism group of the problem Hamiltonian, leading us to develop a circuit construction that is equivariant under this symmetry group. The benefits of our novel circuitstructure, called ORB, are numerically probed in several ground-state problems. We find a consistent improvement (in terms of circuit depth, number of parameters required, and gradient magnitudes) compared to literature circuit constructions.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Impact of K-factor on Short Circuit Program Convergence for Inverter-Based Resources during Faults

Classical short-circuit programs that linearize the power network are no longer applicable for inverter based resources (IBRs), necessitating an iterative approach. Phasor domain programs can model the IBRs using an iterative approach considering nonlinear fault responses. In phasor domain models, the IBR can be modeled as a voltage controlled current source (VCCS) in tabular form with positive, negative, and zero sequence information for balanced and unbalance short-circuit faults. In the VCCS modeling of the IBR, positive and negative incremental reactive current, also known as the k-factor, plays an important role in short circuit program convergence. In this work, a few approaches: conventional VCCS modeling with a k-factor of 2, conventional VCCS modeling with a k-factor of 2 with modified pre-fault voltages, VCCS characteristics based on the power flow solution with a k-factor of 2, and VCCS characteristics based on the power flow solution with a k-factor of 1 are investigated for short circuit program convergence under higher IBR penetration. The IEEE 39 bus New England Test System is taken as the test system, and simulations are carried out in PSS®CAPE 15.0.26 simulation software. Simulation results demonstrate that IBR penetration is higher for the VCCS model, which corresponds to the power flow solution with k-factor 1, compared to other approaches.

42 ENGINEERING↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2022

Pulse-level noisy quantum circuits with QuTiP

The study of the impact of noise on quantum circuits is especially relevant to guide the progress of Noisy Intermediate-Scale Quantum (NISQ) computing. In this paper, we address the pulse-level simulation of noisy quantum circuits with the Quantum Toolbox in Python (QuTiP). We introduce new tools in qutip-qip, QuTiP's quantum information processing package. These tools simulate quantum circuits at the pulse level, leveraging QuTiP's quantum dynamics solvers and control optimization features. We show how quantum circuits can be compiled on simulated processors, with control pulses acting on a target Hamiltonian that describes the unitary evolution of the physical qubits. Various types of noise can be introduced based on the physical model, e.g., by simulating the Lindblad density-matrix dynamics or Monte Carlo quantum trajectories. In particular, the user can define environment-induced decoherence at the processor level and include noise simulation at the level of control pulses. We illustrate how the Deutsch-Jozsa algorithm is compiled and executed on a superconducting-qubit-based processor, on a spin-chain-based processor and using control optimization algorithms. We also show how to easily reproduce experimental results on cross-talk noise in an ion-based processor, and how a Ramsey experiment can be modeled with Lindblad dynamics. Finally, we illustrate how to integrate these features with other software frameworks.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2025

Any Clifford+T circuit can be controlled with constant T-depth overhead

Since an n-qubit circuit consisting of CNOT gates can have up to $Ω(n^2/\log{n})$ CNOT gates, it is natural to expect that $Ω(n^2/\log{n})$ Toffoli gates are needed to apply a controlled version of such a circuit. We show that the Toffoli count can be reduced to at most n. The Toffoli depth can also be reduced to O(1), at the cost of 2n Toffoli gates, even without using any ancilla or measurement. In fact, using a measurement-based uncomputation, the Toffoli depth can be further reduced to 1. From this, we give two corollaries: any controlled Clifford circuit can be implemented with O(1) T-depth, and any Clifford+T circuit with T-depth D can be controlled with T-depth O(D), even without ancillas. As an application, we show how to catalyze a rotation by any angle up to precision $ε$ in T-depth exactly 1 using a universal $\lceil\log_2(8/ε)\rceil$-qubit catalyst state.

FOS: Physical sciences↗
DOE OSTI2019

Input-output processing on a remote integrated circuit chip

An electronic device includes a first integrated circuit chip including a processing functional block, and a second integrated circuit chip including an input-output (IO) functional block. The IO functional block performs one or more IO processing operations on behalf of the processing functional block in the first integrated circuit chip. The first integrated circuit chip lacks at least some elements of the IO functional block, so that the processing functional block is unable to perform corresponding IO operations without the IO functional block.

42 ENGINEERING↗