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At least 163 records · Page 9

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NASA NTRS1989

More on the decoder error probability for Reed-Solomon codes

The decoder error probability for Reed-Solomon codes (more generally, linear maximum distance separable codes) is examined. McEliece and Swanson offered an upper bound on P sub E (u), the decoder error probability given that u symbol errors occur. This upper bound is slightly greater than Q, the probability that a completely random error pattern will cause decoder error. By using a combinatoric technique, the principle of inclusion and exclusion, an exact formula for P sub E (u) is derived. The P sub E (u) for the (255,223) Reed-Solomon Code used by NASA, and for the (31,15) Reed-Solomon code (JTIDS code), are calculated using the exact formula, and the P sub E (u)'s are observed to approach the Q's of the codes rapidly as u gets larger. An upper bound for the expression is derived, and is shown to decrease nearly exponentially as u increases. This proves analytically that P sub E (u) indeed approaches Q as u becomes large, and some laws of large numbers come into play.

Cheung, Kar-Ming↗

NASA NTRS1990

VLSI Architecture For Viterbi Decoder

"Pipeline" architecture developed for very-large-scale integrated (VLSI) Viterbi decoding circuits for binary convolutional codes of large constraint lengths. In scheme, single sequential processor computes path metrics in trellis diagram (diagram in which paths and nodes represent possible sequences of code states and in which metrics indicate relative likelihoods of sequences). Systolic-array method used to store path information as well as to choose path with best metric. VLSI Viterbi-decoder architecture is compromise between speed and complexity. Size of decoding circuit increases approximately linearly with constraint length of code, and additional circuit chips added with moderate numbers of interconnections.

Hsu, In-Shek↗

NASA NTRS1990

Pipeline Time- And Transform-Domain Reed-Solomon Decoders

Modification of decoding algorithms leads to simplified conceptual designs for time- and transform-domain Reed-Soloman (RS) decoders suitable for implementation as very-large-scale integrated (VLSI) circuits. New conceptual decoders determine simultaneously errata-locator and errata-evaluator polynomials as part of simplified scheme for corrections of errors and erasures in RS codes. Highly suitable for implementation in both VLSI circuitry and in software on general-purpose computer.

Hsu, In-Shek↗

NASA NTRS1989

On the decoder error probability of linear codes

By using coding and combinatorial techniques, an approximate formula for the weight distribution of decodable words of most linear block codes is evaluated. This formula is then used to give an approximate expression for the decoder error probability P(sub E)(u) of linear block codes, given that an error pattern of weight u has occurred. It is shown that P(sub E)(u) approaches the constant Q as u gets large, where Q is the probability that a completely random error pattern will cause decoder error.

Cheung, K.-M.↗

NASA NTRS1989

Memory management in traceback Viterbi decoders

The new Viterbi decoder for long constraint length codes, under development for the Deep Space Network, stores path information according to an algorithm called traceback. The details of a particular implementation of this algorithm, based on three memory buffers, are described. The penalties in increased storage requirement and longer decoding delay are offset by the reduced amount of data that needs to be exchanged between processors, in a parallel architecture decoder.

Collins, O.↗

NASA NTRS1989

Big Viterbi Decoder (BVD) results for (7,1/2) convolutional code

The Big Viterbi Decoder (BVD), capable of decoding convolutional codes with constraint lengths of up to 15, is under development for the Deep Space Network (DSN). As part of the development, a commercial single-chip (7,1/2) Viterbi decoder is used to enable early start of system integration. Tests of the integrated partial system (including simulator, input systems, output interfaces, and computer controls) were recently completed at the DSN Compatibility Test Area (CTA-21) at JPL. The system elements used for the demonstration and test results are described.

Statman, J.↗

NASA NTRS1989

Fast transform decoding of nonsystematic Reed-Solomon codes

A Reed-Solomon (RS) code is considered to be a special case of a redundant residue polynomial (RRP) code, and a fast transform decoding algorithm to correct both errors and erasures is presented. This decoding scheme is an improvement of the decoding algorithm for the RRP code suggested by Shiozaki and Nishida, and can be realized readily on very large scale integration chips.

Truong, T. K.↗

NASA NTRS1990

A VLSI design for a systolic Viterbi decoder

A systolic Viterbi decoder for convolutional codes is developed. This decoder uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.

Truong, T. K.↗

NASA NTRS1989

Systolic array processing of the sequential decoding algorithm

A systolic array processing technique is applied to implementing the stack algorithm form of the sequential decoding algorithm. It is shown that sorting, a key function in the stack algorithm, can be efficiently realized by a special type of systolic arrays known as systolic priority queues. Compared to the stack-bucket algorithm, this approach is shown to have the advantages that the decoding always moves along the optimal path, that it has a fast and constant decoding speed and that its simple and regular hardware architecture is suitable for VLSI implementation. Three types of systolic priority queues are discussed: random access scheme, shift register scheme and ripple register scheme. The property of the entries stored in the systolic priority queue is also investigated. The results are applicable to many other basic sorting type problems.

Chang, C. Y.↗

NASA NTRS1992

Compact Spare-Row Decoder For Computer Memory

Spare-row memory-address-decoder circuit commanded to address ninth row in computer memory instead of addressing one of eight others it would address normally. Variants used to construct small, highly reliable computers. Spare-row decoder offers advantages of compactness, efficiency, and performance. Requires only 12.5 percent memory overhead. System equipped with spare-row decoder requires less glue logic and exhibits greater through-put. Applications include computers in Hitchhiker Central Unit embedded computer on Cassini spacecraft. Concept of circuit applicable to most flight computer systems.

Katz, Richard B.↗

NASA NTRS1990

FEC decoder design optimization for mobile satellite communications

A new telecommunications service for location determination via satellite is being proposed for the continental USA and Europe, which provides users with the capability to find the location of, and communicate from, a moving vehicle to a central hub and vice versa. This communications system is expected to operate in an extremely noisy channel in the presence of fading. In order to achieve high levels of data integrity, it is essential to employ forward error correcting (FEC) encoding and decoding techniques in such mobile satellite systems. A constraint length k = 7 FEC decoder has been implemented in a single chip for such systems. The single chip implementation of the maximum likelihood decoder helps to minimize the cost, size, and power consumption, and improves the bit error rate (BER) performance of the mobile earth terminal (MET).

Roy, Ashim↗

NASA NTRS1990

Soft-decision Viterbi decoding with diversity combining

Diversity combining methods for convolutional coded and soft-decision Viterbi decoded channels in mobile satellite communications systems are evaluated and it is clarified that the pre-Viterbi-decoding maximal ratio combining shows better performance than other methods in Rician fading channels by computer simulation. A novel practical technique for maximal ratio combining is proposed, in which the coefficients for weighting are derived from soft-decision demodulated signals only. The proposed diversity combining method with soft-decision Viterbi decoding requires simple hardware and shows satisfactory performance with slight degradation of 0.3 dB in Rician fading channels compared with an ideal weighting scheme. Furthermore, this diversity method is applied to trellis coded modulation and significant Pe performance improvement is achieved.

Sakai, T.↗

NASA NTRS1992

Node synchronization schemes for the Big Viterbi Decoder

The Big Viterbi Decoder (BVD), currently under development for the DSN, includes three separate algorithms to acquire and maintain node and frame synchronization. The first measures the number of decoded bits between two consecutive renormalization operations (renorm rate), the second detects the presence of the frame marker in the decoded bit stream (bit correlation), while the third searches for an encoded version of the frame marker in the encoded input stream (symbol correlation). A detailed account of the operation is given, as well as performance comparison, of the three methods.

Cheung, K.-M.↗

NASA NTRS1991

Suboptimum decoding of block codes

This paper investigates a class of decomposable codes, their distance and structural properties. it is shown that this class includes several classes of well known and efficient codes as subclasses. Several methods for constructing decomposable codes or decomposing codes are presented. A two-stage soft decision decoding scheme for decomposable codes, their translates or unions of translates is devised. This two-stage soft-decision decoding is suboptimum, and provides an excellent trade-off between the error performance and decoding complexity for codes of moderate and long block length.

Lin, Shu↗

NASA NTRS1991

An extended Reed Solomon decoder design

It has previously been shown that the Reed-Solomon (RS) codes can correct errors beyond the Singleton and Rieger Bounds with an arbitrarily small probability of a miscorrect. That is, an (n,k) RS code can correct more than (n-k)/2 errors. An implementation of such an RS decoder is presented in this paper. An existing RS decoder, the AHA4010, is utilized in this work. This decoder is especially useful for errors which are patterned with a long burst plus some random errors.

Chen, J.↗

NASA NTRS1993

Multichannel error correction code decoder

A brief overview of a processing satellite for a mesh very-small-aperture (VSAT) communications network is provided. The multichannel error correction code (ECC) decoder system, the uplink signal generation and link simulation equipment, and the time-shared decoder are described. The testing is discussed. Applications of the time-shared decoder are recommended.

Wagner, Paul K.↗

NASA NTRS1996

An Iterative Soft-Decision Decoding Algorithm

This paper presents a new minimum-weight trellis-based soft-decision iterative decoding algorithm for binary linear block codes. Simulation results for the RM(64,22), EBCH(64,24), RM(64,42) and EBCH(64,45) codes show that the proposed decoding algorithm achieves practically (or near) optimal error performance with significant reduction in decoding computational complexity. The average number of search iterations is also small even for low signal-to-noise ratio.

Lin, Shu↗

NASA NTRS1998

Investigation of Different Constituent Encoders in a Turbo-code Scheme for Reduced Decoder Complexity

A large number of papers have been published attempting to give some analytical basis for the performance of Turbo-codes. It has been shown that performance improves with increased interleaver length. Also procedures have been given to pick the best constituent recursive systematic convolutional codes (RSCC's). However testing by computer simulation is still required to verify these results. This thesis begins by describing the encoding and decoding schemes used. Next simulation results on several memory 4 RSCC's are shown. It is found that the best BER performance at low E(sub b)/N(sub o) is not given by the RSCC's that were found using the analytic techniques given so far. Next the results are given from simulations using a smaller memory RSCC for one of the constituent encoders. Significant reduction in decoding complexity is obtained with minimal loss in performance. Simulation results are then given for a rate 1/3 Turbo-code with the result that this code performed as well as a rate 1/2 Turbo-code as measured by the distance from their respective Shannon limits. Finally the results of simulations where an inaccurate noise variance measurement was used are given. From this it was observed that Turbo-decoding is fairly stable with regard to noise variance measurement.

Kwatra, S. C.↗