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At least 163 records · Page 9

Systolic array processing of the sequential decoding algorithm

A systolic array processing technique is applied to implementing the stack algorithm form of the sequential decoding algorithm. It is shown that sorting, a key function in the stack algorithm, can be efficiently realized by a special type of systolic arrays known as systolic priority queues. Compared to the stack-bucket algorithm, this approach is shown to have the advantages that the decoding always moves along the optimal path, that it has a fast and constant decoding speed and that its simple and regular hardware architecture is suitable for VLSI implementation. Three types of systolic priority queues are discussed: random access scheme, shift register scheme and ripple register scheme. The property of the entries stored in the systolic priority queue is also investigated. The results are applicable to many other basic sorting type problems.

Chang, C. Y.↗

Compact Spare-Row Decoder For Computer Memory

Spare-row memory-address-decoder circuit commanded to address ninth row in computer memory instead of addressing one of eight others it would address normally. Variants used to construct small, highly reliable computers. Spare-row decoder offers advantages of compactness, efficiency, and performance. Requires only 12.5 percent memory overhead. System equipped with spare-row decoder requires less glue logic and exhibits greater through-put. Applications include computers in Hitchhiker Central Unit embedded computer on Cassini spacecraft. Concept of circuit applicable to most flight computer systems.

Katz, Richard B.↗

FEC decoder design optimization for mobile satellite communications

A new telecommunications service for location determination via satellite is being proposed for the continental USA and Europe, which provides users with the capability to find the location of, and communicate from, a moving vehicle to a central hub and vice versa. This communications system is expected to operate in an extremely noisy channel in the presence of fading. In order to achieve high levels of data integrity, it is essential to employ forward error correcting (FEC) encoding and decoding techniques in such mobile satellite systems. A constraint length k = 7 FEC decoder has been implemented in a single chip for such systems. The single chip implementation of the maximum likelihood decoder helps to minimize the cost, size, and power consumption, and improves the bit error rate (BER) performance of the mobile earth terminal (MET).

Roy, Ashim↗

Soft-decision Viterbi decoding with diversity combining

Diversity combining methods for convolutional coded and soft-decision Viterbi decoded channels in mobile satellite communications systems are evaluated and it is clarified that the pre-Viterbi-decoding maximal ratio combining shows better performance than other methods in Rician fading channels by computer simulation. A novel practical technique for maximal ratio combining is proposed, in which the coefficients for weighting are derived from soft-decision demodulated signals only. The proposed diversity combining method with soft-decision Viterbi decoding requires simple hardware and shows satisfactory performance with slight degradation of 0.3 dB in Rician fading channels compared with an ideal weighting scheme. Furthermore, this diversity method is applied to trellis coded modulation and significant Pe performance improvement is achieved.

Sakai, T.↗

Node synchronization schemes for the Big Viterbi Decoder

The Big Viterbi Decoder (BVD), currently under development for the DSN, includes three separate algorithms to acquire and maintain node and frame synchronization. The first measures the number of decoded bits between two consecutive renormalization operations (renorm rate), the second detects the presence of the frame marker in the decoded bit stream (bit correlation), while the third searches for an encoded version of the frame marker in the encoded input stream (symbol correlation). A detailed account of the operation is given, as well as performance comparison, of the three methods.

Cheung, K.-M.↗

Suboptimum decoding of block codes

This paper investigates a class of decomposable codes, their distance and structural properties. it is shown that this class includes several classes of well known and efficient codes as subclasses. Several methods for constructing decomposable codes or decomposing codes are presented. A two-stage soft decision decoding scheme for decomposable codes, their translates or unions of translates is devised. This two-stage soft-decision decoding is suboptimum, and provides an excellent trade-off between the error performance and decoding complexity for codes of moderate and long block length.

Lin, Shu↗

An extended Reed Solomon decoder design

It has previously been shown that the Reed-Solomon (RS) codes can correct errors beyond the Singleton and Rieger Bounds with an arbitrarily small probability of a miscorrect. That is, an (n,k) RS code can correct more than (n-k)/2 errors. An implementation of such an RS decoder is presented in this paper. An existing RS decoder, the AHA4010, is utilized in this work. This decoder is especially useful for errors which are patterned with a long burst plus some random errors.

Chen, J.↗

Multichannel error correction code decoder

A brief overview of a processing satellite for a mesh very-small-aperture (VSAT) communications network is provided. The multichannel error correction code (ECC) decoder system, the uplink signal generation and link simulation equipment, and the time-shared decoder are described. The testing is discussed. Applications of the time-shared decoder are recommended.

Wagner, Paul K.↗

An Iterative Soft-Decision Decoding Algorithm

This paper presents a new minimum-weight trellis-based soft-decision iterative decoding algorithm for binary linear block codes. Simulation results for the RM(64,22), EBCH(64,24), RM(64,42) and EBCH(64,45) codes show that the proposed decoding algorithm achieves practically (or near) optimal error performance with significant reduction in decoding computational complexity. The average number of search iterations is also small even for low signal-to-noise ratio.

Lin, Shu↗

Investigation of Different Constituent Encoders in a Turbo-code Scheme for Reduced Decoder Complexity

A large number of papers have been published attempting to give some analytical basis for the performance of Turbo-codes. It has been shown that performance improves with increased interleaver length. Also procedures have been given to pick the best constituent recursive systematic convolutional codes (RSCC's). However testing by computer simulation is still required to verify these results. This thesis begins by describing the encoding and decoding schemes used. Next simulation results on several memory 4 RSCC's are shown. It is found that the best BER performance at low E(sub b)/N(sub o) is not given by the RSCC's that were found using the analytic techniques given so far. Next the results are given from simulations using a smaller memory RSCC for one of the constituent encoders. Significant reduction in decoding complexity is obtained with minimal loss in performance. Simulation results are then given for a rate 1/3 Turbo-code with the result that this code performed as well as a rate 1/2 Turbo-code as measured by the distance from their respective Shannon limits. Finally the results of simulations where an inaccurate noise variance measurement was used are given. From this it was observed that Turbo-decoding is fairly stable with regard to noise variance measurement.

Kwatra, S. C.↗

Decoding Ca2+ signals in plants

Different input signals create their own characteristic Ca2+ fingerprints. These fingerprints are distinguished by frequency, amplitude, duration, and number of Ca2+ oscillations. Ca(2+)-binding proteins and protein kinases decode these complex Ca2+ fingerprints through conformational coupling and covalent modifications of proteins. This decoding of signals can lead to a physiological response with or without changes in gene expression. In plants, Ca(2+)-dependent protein kinases and Ca2+/calmodulin-dependent protein kinases are involved in decoding Ca2+ signals into phosphorylation signals. This review summarizes the elements of conformational coupling and molecular mechanisms of regulation of the two groups of protein kinases by Ca2+ and Ca2+/calmodulin in plants.

Non-NASA Center↗

Method and apparatus for implementing a maximum-likelihood decoder in a hypercube network

A method and a structure to implement maximum-likelihood decoding of convolutional codes on a network of microprocessors interconnected as an n-dimensional cube (hypercube). By proper reordering of states in the decoder, only communication between adjacent processors is required. Faster and more efficient operation is enabled, and decoding of large constraint length codes is feasible using standard VLSI technology.

Pollara-Bozzola, Fabrizio↗

Large constraint length high speed viterbi decoder based on a modular hierarchial decomposition of the deBruijn graph

A method of formulating and packaging decision-making elements into a long constraint length Viterbi decoder which involves formulating the decision-making processors as individual Viterbi butterfly processors that are interconnected in a deBruijn graph configuration. A fully distributed architecture, which achieves high decoding speeds, is made feasible by novel wiring and partitioning of the state diagram. This partitioning defines universal modules, which can be used to build any size decoder, such that a large number of wires is contained inside each module, and a small number of wires is needed to connect modules. The total system is modular and hierarchical, and it implements a large proportion of the required wiring internally within modules and may include some external wiring to fully complete the deBruijn graph. pg,14.

Collins, Oliver↗

Joint Carrier-Phase Synchronization and LDPC Decoding

A method has been proposed to increase the degree of synchronization of a radio receiver with the phase of a suppressed carrier signal modulated with a binary- phase-shift-keying (BPSK) or quaternary- phase-shift-keying (QPSK) signal representing a low-density parity-check (LDPC) code. This method is an extended version of the method described in Using LDPC Code Constraints to Aid Recovery of Symbol Timing (NPO-43112), NASA Tech Briefs, Vol. 32, No. 10 (October 2008), page 54. Both methods and the receiver architectures in which they would be implemented belong to a class of timing- recovery methods and corresponding receiver architectures characterized as pilotless in that they do not require transmission and reception of pilot signals. The proposed method calls for the use of what is known in the art as soft decision feedback to remove the modulation from a replica of the incoming signal prior to feeding this replica to a phase-locked loop (PLL) or other carrier-tracking stage in the receiver. Soft decision feedback refers to suitably processed versions of intermediate results of iterative computations involved in the LDPC decoding process. Unlike a related prior method in which hard decision feedback (the final sequence of decoded symbols) is used to remove the modulation, the proposed method does not require estimation of the decoder error probability. In a basic digital implementation of the proposed method, the incoming signal (having carrier phase theta theta (sub c) plus noise would first be converted to inphase (I) and quadrature (Q) baseband signals by mixing it with I and Q signals at the carrier frequency [wc/(2 pi)] generated by a local oscillator. The resulting demodulated signals would be processed through one-symbol-period integrate and- dump filters, the outputs of which would be sampled and held, then multiplied by a soft-decision version of the baseband modulated signal. The resulting I and Q products consist of terms proportional to the cosine and sine of the carrier phase cc as well as correlated noise components. These products would be fed as inputs to a digital PLL that would include a number-controlled oscillator (NCO), which provides an estimate of the carrier phase, theta(sub c).

Simon, Marvin↗

VLSI Design of a Turbo Decoder

A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

Fang, Wai-Chi↗

Generalized minimum distance decoding.

Generalized minimum distance decoding that permits likelihood information to be used, yielding same probability of error as maximum likelihood decoding

DISTANCE MEASURING EQUIPMENT↗

Maximum likelihood decoding analysis of accumulate-repeat-accumulate codes

In this paper, the performance of the repeat-accumulate codes with (ML) decoding are analyzed and compared to random codes by very tight bounds. Some simple codes are shown that perform very close to Shannon limit with maximum likelihood decoding.

LDPC codes turbo-like codes maximum likelihood dec↗

Deep Space Network turbo decoder implementation

A new decoder is being developed by the Jet Propulsion Laboratory for NASA's Deep Space Network. This unit will decode the new turbo codes, which have recently been approved by the Consultative Committee for Space Data Systems (CCSDS).

turbo decoder turbo code↗