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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
NASA NTRS2019

Lynx x-ray microcalorimeter

Lynx is an x-ray telescope, one of four large satellite mission concepts currently being studied by NASA to be a flagship mission. One of Lynx’s three instruments is an imaging spectrometer called the Lynx x-ray microcalorimeter (LXM), an x-ray microcalorimeter behind an x-ray optic with an angular resolution of 0.5 arc sec and ∼2 sq. m of area at 1 keV. The LXM will provide unparalleled diagnostics of distant extended structures and, in particular, will allow the detailed study of the role of cosmic feedback in the evolution of the Universe. We discuss the baseline design of LXM and some parallel approaches for some of the key technologies. The baseline sensor technology uses transition-edge sensors, but we also consider an alternative approach using metallic magnetic calorimeters. We discuss the requirements for the instrument, the pixel layout, and the baseline readout design, which uses microwave superconducting quantum interference devices and high-electron mobility transistor amplifiers and the cryogenic cooling requirements and strategy for meeting these requirements. For each of these technologies, we discuss the current technology readiness level and our strategy for advancing them to be ready for flight. We also describe the current system design, including the block diagram, and our estimate for the mass, power, and data rate of the instrument.

Simon R. Bandler↗
NASA NTRS2020

X- to Ka- Band Cryogenic LNA Module for Very Long Baseline Interferometry

We report a new result of a packaged low noise amplifier (LNA) module with wide bandwidth of 5 to 35 GHz with low noise temperature performance of 10 - 18 K, while operated at 10 K ambient. The LNA used 3-stages of sub-50 nm gate length, 100% indium channel content indium phosphide (InP) high electron mobility transistors (HEMTs). Wideband cryogenic LNAs are important for future radio astronomy observatories. To our knowledge these results represent the lowest noise achieved in a wideband amplifier from 5-35 GHz.

Fung, Andy↗
NASA NTRSDate not supplied

A Spectrally Efficient Ka-Band GaN Power Amplifier with Scalable Power Combining Architecture for Lunar High Data Rate Direct-to-Earth Communications

The output power from a single gallium nitride (GaN) high electron mobility transistor (HEMT) based monolithic microwave integrated circuit (MMIC) power amplifier (PA) chip is limited to few watts. To achieve higher power, the output from several chips have to be combined. In this paper we present, the results of a study conducted to investigate a 2-way power combiner to combine the output power from two GaN MMIC based high power amplifier (HPA) chips The parameters investigated includes the power combiner characteristics, individual GaN MMIC based HPA output power, gain, and power added efficiency, and the overall performance of the combined amplifier.

Gallium Nitride↗
NASA NTRS1988

Electron beam source molecular beam epitaxial growth of analog graded Al(x)Ga(1-x)As ballistic transistors

A new method has been developed for the growth of graded band-gap Al(x)Ga(1-x)As alloys by molecular beam epitaxy which is based upon electron beam evaporation of the group III elements. The metal fluxes are measured and feedback controlled using a modulated ion gauge sensor. The system is computer controlled which allows precise programming of the Ga and Al evaporation rates. The large dynamic response of the metal sources enables growth of variable band-gap III-V alloys with arbitrary composition profiles. This new technique is demonstrated by synthesis of analog graded Al(x)Ga(1-x)As unipolar ballistic electron transistors.

Malik, Roger J.↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
NASA NTRS2016

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

Body of Knowledge (BOK)↗
NASA NTRS2007

CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

Yeh, Penshu↗
NASA NTRS2006

MMIC DHBT Common-Base Amplifier for 172 GHz

Figure 1 shows a single-stage monolithic microwave integrated circuit (MMIC) power amplifier in which the gain element is a double-heterojunction bipolar transistor (DHBT) connected in common-base configuration. This amplifier, which has been demonstrated to function well at a frequency of 172 GHz, is part of a continuing effort to develop compact, efficient amplifiers for scientific instrumentation, wide-band communication systems, and radar systems that will operate at frequencies up to and beyond 180 GHz. The transistor is fabricated from a layered structure formed by molecular beam epitaxy in the InP/InGaAs material system. A highly doped InGaAs base layer and a collector layer are fabricated from the layered structure in a triple mesa process. The transistor includes two separate emitter fingers, each having dimensions of 0.8 by 12 m. The common-base configuration was chosen for its high maximum stable gain in the frequency band of interest. The input-matching network is designed for high bandwidth. The output of the transistor is matched to a load line for maximum saturated output power under large-signal conditions, rather than being matched for maximum gain under small-signal conditions. In a test at a frequency of 172 GHz, the amplifier was found to generate an output power of 7.5 mW, with approximately 5 dB of large-signal gain (see Figure 2). Moreover, the amplifier exhibited a peak small-signal gain of 7 dB at a frequency of 176 GHz. This performance of this MMIC single-stage amplifier containing only a single transistor represents a significant advance in the state of the art, in that it rivals the 170-GHz performance of a prior MMIC three-stage, four-transistor amplifier. [The prior amplifier was reported in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11 (November 2003), page 49.] This amplifier is the first heterojunction- bipolar-transistor (HBT) amplifier built for medium power operation in this frequency band. The performance of the amplifier as measured in the aforementioned tests suggests that InP/InGaAs HBTs may be superior to high-electron-mobility (HEMT) transistors in that the HBTs may offer more gain per stage and more output power per transistor.

Paidi, Vamsi↗
NASA NTRS2012

SiGe Based Low Temperature Electronics for Lunar Surface Applications

The temperature at the permanently shadowed regions of the moon's surface is approximately -240 C. Other areas of the lunar surface experience temperatures that vary between 120 C and -180 C during the day and night respectively. To protect against the large temperature variations of the moon surface, traditional electronics used in lunar robotics systems are placed inside a thermally controlled housing which is bulky, consumes power and adds complexity to the integration and test. SiGe Based electronics have the capability to operate over wide temperature range like that of the lunar surface. Deploying low temperature SiGe electronics in a lander platform can minimize the need for the central thermal protection system and enable the development of a new generation of landers and mobility platforms with highly efficient distributed architecture. For the past five years a team consisting of NASA, university and industry researchers has been examining the low temperature and wide temperature characteristic of SiGe based transistors for developing electronics for wide temperature needs of NASA environments such as the Moon, Titan, Mars and Europa. This presentation reports on the status of the development of wide temperature SiGe based electronics for the landers and lunar surface mobility systems.

electonics↗
NASA NTRS2009

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Patterson, Richard↗
NASA NTRS1976

Method and apparatus for measurement of trap density and energy distribution in dielectric films

Trap densities in dielectric films are determined by tunnel injection measurements when the film is incorporated in an insulated-gate field effect transistor. Under applied bias to the transistor gate, carriers (electrons or holes) tunnel into traps in the dielectric film. The resulting space charge tends to change channel conductance. By feeding back a signal from the source contact to the gate electrode, channel conductance is held constant, and by recording the gate voltage as a function of time, trap density can be determined as a function of distance from the dielectric-semiconductor interface. The process is repeated with the gate bias voltage at different levels in order to determine the energy distribution of traps as a function of distance from the interface.

Maserjian, J.↗
NASA NTRS2000

Temperature Distribution Within a Defect-Free Silicon Carbide Diode Predicted by a Computational Model

Most solid-state electronic devices diodes, transistors, and integrated circuits are based on silicon. Although this material works well for many applications, its properties limit its ability to function under extreme high-temperature or high-power operating conditions. Silicon carbide (SiC), with its desirable physical properties, could someday replace silicon for these types of applications. A major roadblock to realizing this potential is the quality of SiC material that can currently be produced. Semiconductors require very uniform, high-quality material, and commercially available SiC tends to suffer from defects in the crystalline structure that have largely been eliminated in silicon. In some power circuits, these defects can focus energy into an extremely small area, leading to overheating that can damage the device. In an effort to better understand the way that these defects affect the electrical performance and reliability of an SiC device in a power circuit, the NASA Glenn Research Center at Lewis Field began an in-house three-dimensional computational modeling effort. The goal is to predict the temperature distributions within a SiC diode structure subjected to the various transient overvoltage breakdown stresses that occur in power management circuits. A commercial computational fluid dynamics computer program (FLUENT-Fluent, Inc., Lebanon, New Hampshire) was used to build a model of a defect-free SiC diode and generate a computational mesh. A typical breakdown power density was applied over 0.5 msec in a heated layer at the junction between the p-type SiC and n-type SiC, and the temperature distribution throughout the diode was then calculated. The peak temperature extracted from the computational model agreed well (within 6 percent) with previous first-order calculations of the maximum expected temperature at the end of the breakdown pulse. This level of agreement is excellent for a model of this type and indicates that three-dimensional computational modeling can provide useful predictions for this class of problem. The model is now being extended to include the effects of crystal defects. The model will provide unique insights into how high the temperature rises in the vicinity of the defects in a diode at various power densities and pulse durations. This information also will help researchers in understanding and designing SiC devices for safe and reliable operation in high-power circuits.

Kuczmarski, Maria A.↗