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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Solid-state reprogrammable analog resistive devices for electronic neural networks

The fabrication and performance of WO3-based, solid-state, three-terminal device configurations as programmable analog memory elements are reported. These transistorlike device structures exhibit good resistance progammability with a remarkable resolution of a few percent of the resistive strength over a four orders of magnitude dynamic range. The most critical component of these devices is an insulating layer between the active WO3 and the cation donor layer. The progamming characteristics and operation mechanisms of the device are described, and probable reaction mechanisms critical to the device stability are discussed.

Ramesham, R.↗
NASA NTRS2004

Portable Integrated Wireless Device Threat Assessment to Aircraft Radio Systems

An assessment was conducted on multiple wireless local area network (WLAN) devices using the three wireless standards for spurious radiated emissions to determine their threat to aircraft radio navigation systems. The measurement process, data and analysis are provided for devices tested using IEEE 802.11a, IEEE 802.11b, and Bluetooth as well as data from portable laptops/tablet PCs and PDAs (grouping known as PEDs). A comparison was made between wireless LAN devices and portable electronic devices. Spurious radiated emissions were investigated in the radio frequency bands for the following aircraft systems: Instrument Landing System Localizer and Glideslope, Very High Frequency (VHF) Communication, VHF Omnidirectional Range, Traffic Collision Avoidance System, Air Traffic Control Radar Beacon System, Microwave Landing System and Global Positioning System. Since several of the contiguous navigation systems were grouped under one encompassing measurement frequency band, there were five measurement frequency bands where spurious radiated emissions data were collected for the PEDs and WLAN devices. The report also provides a comparison between emissions data and regulatory emission limit.

Salud, Maria Theresa P.↗
DOE OSTI2023

Connector interface assembly for enclosed vessels and associated systems and methods

Systems, methods, and apparatus that employ a connector assembly having a substrate layer with an inner aperture and an outer periphery, and one or more signal traces disposed on the substrate that extend from an inner first location to an outer second location of the apparatus, for communicating data between electronic devices positioned within an interior volume of an enclosed vessel and complementary electronic devices positioned in an ambient environment external to the enclosed vessel. An inner connector is conductively connected the signal traces at the inner first location of each signal trace, and an outer connector is conductively connected to the one or more signal traces at the outer second location of each signal trace. A substantially flat exterior surface extends radially over at least a portion of a region between the respective first locations and the respective second locations.

Estrada, Juan↗
DOE OSTI2022

An implantable biomechanical energy harvester for animal monitoring devices

Insufficient service life and the resulting need for battery replacements have been a great challenge for implantable electronic devices. This is particularly true for animal tracking applications, because recapturing animals is often unlikely once they are released to the wild. To tackle this problem, we developed a biomechanical energy harvester that uses a Macro Fiber Composite™ (MFC) piezoelectric beam to harvest the mechanical energy from animals’ body bending movements as the power source for implantable and wearable devices. Prototypes of an underwater acoustic transmitter using this technology were subdermally implanted into juvenile white sturgeon and their energy harvesting performance was evaluated through the device’s transmissions. Additionally, the fish successfully recovered from the implantation surgery and freely swam inside a tank. The transmitter prototypes in the fish continually transmitted signals for a period up to 5 weeks. A benchtop test setup was also created to emulate the fish’s body bending, estimate the device’s energy harvesting performance in the live fish, and perform accelerated fatigue testing of the energy harvester by applying test parameters learned from a video study of the fish’s body movement and behavior characteristics. The gradual depolarization of the piezoelectric ceramic material in the MFC under cyclic mechanical loading was the main limiting factor for the life span of the energy harvester. Pathways for improvement are proposed to achieve long-term efficacy of powering implantable and wearable electronic devices.

42 ENGINEERING↗
DOE OSTI2023

Superconducting bilayers of two-dimensional materials with integrated Josephson junctions

Josephson junctions (JJ) based on bilayers of azimuthally misaligned two-dimensional materials having superconducting states are provided. Also provided are electronic devices and circuits incorporating the JJs as active components and methods of using the electronic devices and circuits. The JJs are formed from bilayers composed of azimuthally misaligned two-dimensional materials having a first superconducting segment and a second superconducting segment separated by a weak-link region that is integrated into the bilayer.

Lagally, Max G.↗
NASA NTRS1999

Die Attachment for -120 C to +20 C Thermal Cycling of Microelectronics for Future Mars Rovers: An Overview

Active thermal control for electronics on Mars Rovers imposes a serious penalty in weight, volume, power consumption, and reliability. Thus, we propose that thermal control be eliminated for future Rovers. From a functional standpoint there is no reason that the electronics could not operate over the entire temperature range of the Martian environment, which can vary from a low of approximately equal -90 C to a high of approximately equal +20 C during the Martian night and day. The upper end of this range is well within that for conventional electronics. Although the lower end is considerably below that for which conventional--even high-reliability electronics is designed or tested, it is well established that electronic devices can operate to such low temperatures. The primary concern is reliability of the overall electronic system, especially in regard to the numerous daily temperature cycles that it would experience over the duration of a mission on Mars. Accordingly, key reliability issues have been identified for elimination of thermal control on future Mars Rovers. One of these is attachment of semiconductor die onto substrates and into packages. Die attachment is critical since it forms a mechanical, thermal and electrical interface between the electronic device and the substrate or package. This paper summarizes our initial investigation of existing information related to this issue, in order to form an opinion whether die attachment techniques exist, or could be developed with reasonable effort, to withstand the Mars thermal environment for a mission duration of approximately I year. Our conclusion, from a review of literature and personal contacts. is that die attachment can be made sufficiently reliable to satisfy the requirements of future Mars Rovers. Moreover, it appears that there are several possible techniques from which to choose and that the requirements could be met by judicious selection from existing methods using hard solders, soft solders, or organic adhesives. Thus from the standpoint of die attachment. it appears feasible to eliminate thermal control for Rover electronics. We recommend that this be further investigated and verified for the specific hardware and thermal conditions appropriate to Mars Rovers.

Kirschman, Randall K.↗
DOE OSTI2020

Intra-microgrid communication architecture

A microgrid according to an exemplary aspect of the present disclosure includes, among other things, a plurality of intelligent electronic devices configured to communicate directly with one another in a first language. Each of the intelligent electronic devices includes a controller and a gateway. The gateway is configured to convert incoming messages from the first language to a second language native to the controller. The first language is different than the second language. A method is also disclosed.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Controlling accesses to a branch prediction unit for sequences of fetch groups

An electronic device handles accesses of a branch prediction functional block when executing instructions in program code. The electronic device includes a processor having the branch prediction functional block that provides branch prediction information for control transfer instructions (CTIs) in the program code and a minimum predictor use (MPU) functional block. The MPU functional block determines, based on a record associated with a given fetch group of instructions, that a specified number of subsequent fetch groups of instructions that were previously determined to include no CTIs or conditional CTIs that were not taken are to be fetched for execution in sequence following the given fetch group. The MPU functional block then, when each of the specified number of the subsequent fetch groups is fetched and prepared for execution, prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that subsequent fetch group.

Agrawal, Varun↗
DOE OSTI2022

Controlling accesses to a branch prediction unit for sequences of fetch groups

An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

Yalavarti, Adithya↗
DOE OSTI2021

Preprocessing for Unintended Conducted Emissions Classification with ResNet

Characterization of Unintended Conducted Emissions (UCE) from electronic devices is important when diagnosing electromagnetic interference, performing nonintrusive load monitoring (NILM) of power systems, and monitoring electronic device health, among other applications. Prior work has demonstrated that UCE analysis can serve as a diagnostic tool for energy efficiency investigations and detailed load analysis. While explaining the feature selection of deep networks with certainty is often not fully comprehensive, or in other applications, quite lacking, additional tools/methods for further corroboration and confirmation can help further the understanding of the researcher. This is true especially in the subject application of the study in this paper. Often the focus of such efforts is the selected features themselves, and there is not as much understanding gained about the noise in the collected data. If selected feature and noise characteristics are known, it can be used to further shape the design of the deep network or associated preprocessing. This is additionally difficult when the available data are limited, as in the case which the authors investigated in this study. Here, the authors present a novel work (which is a proposed complementary portion of the overall solution to the deep network classification explainability problem for this application) by applying a systematic progression of preprocessing and a deep neural network (ResNet architecture) to classify UCE data obtained via current transformers. By using a methodical application of preprocessing techniques prior to a deep classifier, hypotheses can be produced concerning what features the deep network deems important relative to what it perceives as noise. For instance, it is hypothesized in this particular study as a result of execution of the proposed method and periodic inspection of the classifier output that the UCE spectral features are relatively close to each other or to the interferers, as systematically reducing the beta parameter of the Kaiser window produced progressively better classification performance, but only to a point, as going below the Beta of eight produced decreased classifier performance, as well as the hypothesis that further spectral feature resolution was not as important to the classifier as rejection of the leakage from a spectrally distant interference. This can be very important in unpredictable low-FNR applications, where knowing the difference between features and noise is difficult. As a side-benefit, much was learned regarding the best preprocessing to use with the selected deep network for the UCE collected from these low power consumer devices obtained via current transformers. Baseline rectangular windowed FFT preprocessing provided a 62% classification increase versus using raw samples. After performing a more optimal preprocessing, more than 90% classification accuracy was achieved across 18 low-power consumer devices for scenarios in which the in-band features-to-noise ratio (FNR) was very poor.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
NASA NTRS1998

Simulation of Ultra-Small MOSFETs Using a 2-D Quantum-Corrected Drift-Diffusion Model

The continued down-scaling of electronic devices, in particular the commercially dominant MOSFET, will force a fundamental change in the process of new electronics technology development in the next five to ten years. The cost of developing new technology generations is soaring along with the price of new fabrication facilities, even as competitive pressure intensifies to bring this new technology to market faster than ever before. To reduce cost and time to market, device simulation must become a more fundamental, indeed dominant, part of the technology development cycle. In order to produce these benefits, simulation accuracy must improve markedly. At the same time, device physics will become more complex, with the rapid increase in various small-geometry and quantum effects. This work describes both an approach to device simulator development and a physical model which advance the effort to meet the tremendous electronic device simulation challenge described above. The device simulation approach is to specify the physical model at a high level to a general-purpose (but highly efficient) partial differential equation solver (in this case PROPHET, developed by Lucent Technologies), which then simulates the model in 1-D, 2-D, or 3-D for a specified device and test regime. This approach allows for the rapid investigation of a wide range of device models and effects, which is certainly essential for device simulation to catch up with, and then stay ahead of, electronic device technology of the present and future. The physical device model used in this work is the density-gradient (DG) quantum correction to the drift-diffusion model [Ancona, Phys. Rev. B 35(5), 7959 (1987)]. This model adds tunneling and quantum smoothing of carrier density profiles to the drift-diffusion model. We used the DG model in 1-D and 2-D (for the first time) to simulate both bipolar and unipolar devices. Simulations of heavily-doped, short-base diodes indicated that the DG quantum corrections do not have a large effect on the IN characteristics of electronic devices without heteroj unction s. On the other hand, ultra-small MOSFETs certainly exhibit important quantum effects that the DG model will include: quantum repulsion of the inversion and gate charges from the oxide interfaces, and quantum tunneling through thin gate oxides. We present initial results of 2-D DG simulations of ultra-small MOSFETs. Subtle but important issues involving the specification of the model, boundary conditions, and interface constraints for DG simulation of MOSFETs will also be illuminated.

Biegal, Bryan A.↗
NASA NTRS2008

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗
DOE OSTI2023

Bottom-up synthesis of mesoscale nanomeshes of graphene nanoribbons on germanium

The synthesis of functional graphene nanostructures on Ge(001) provides an attractive route toward integrating graphene-based electronic devices onto complementary metal oxide semiconductor-compatible platforms. In this study, we leverage the phenomenon of the anisotropic growth of graphene nanoribbons from rationally placed graphene nanoseeds and their rotational self-alignment during chemical vapor deposition to synthesize mesoscale graphene nanomeshes over areas spanning several hundred square micrometers. Lithographically patterned nanoseeds are defined on a Ge(001) surface at pitches ranging from 50 to 100 nm, which serve as starting sites for subsequent nanoribbon growth. Rotational self-alignment of the nanoseeds followed by anisotropic growth kinetics causes the resulting nanoribbons to be oriented along each of the equivalent, orthogonal Ge < 110 > directions with equal probability. As the nanoribbons grow, they fuse, creating a continuous nanomesh. In contrast to nanomesh synthesis via top-down approaches, this technique yields nanomeshes with atomically faceted edges and covalently bonded junctions, which are important for maximizing charge transport properties. Additionally, we simulate the electrical characteristics of nanomeshes synthesized from different initial nanoseed-sizes, size-polydispersities, pitches, and device channel lengths to identify a parameter-space for acceptable on/off ratios and on-conductance in semiconductor electronics. The simulations show that decreasing seed diameter and pitch are critical to increasing nanomesh on/off ratio and on-conductance, respectively. With further refinements in lithography, nanomeshes obtained via seeded synthesis and anisotropic growth are likely to have superior electronic properties with tremendous potential in a multitude of applications, such as radio frequency communications, sensing, thin-film electronics, and plasmonics.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2021

Transfer-Free Synthesis of Atomically Precise Graphene Nanoribbons on Insulating Substrates

The rational bottom-up synthesis of graphene nanoribbons (GNRs) provides atomically precise control of widths and edges that give rise to a wide range of electronic properties promising for electronic devices such as field-effect transistors (FETs). Since the bottom-up synthesis commonly takes place on catalytic metallic surfaces, the integration of GNRs into such devices requires their transfer onto insulating substrates, which remains one of the bottlenecks in the development of GNR-based electronics. Herein, we report on a method for the transfer-free placement of GNRs on insulators. This involves growing GNRs on a gold film deposited onto an insulating layer followed by gentle wet etching of the gold, which leaves the nanoribbons to settle in place on the underlying insulating substrate. Scanning tunneling microscopy and Raman spectroscopy confirm that atomically precise GNRs of high density uniformly grow on the gold films deposited onto SiO 2 /Si substrates and remain structurally intact after the etching process. We have also demonstrated transfer-free fabrication of ultrashort channel GNR FETs using this process. A very important aspect of the present work is that the method can scale up well to 12 in. wafers, which is extremely difficult for previous techniques. Our work here thus represents an important step toward large-scale integration of GNRs into electronic devices.

36 MATERIALS SCIENCE↗
NASA NTRS2004

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Speer, Kevin M.↗
DOE OSTI2022

Switching charge states in quasi-2D molecular conductors

Abstract 2D molecular entities build next-generation electronic devices, where abundant elements of organic molecules are attractive due to the modern synthetic and stimuli control through chemical, conformational, and electronic modifications in electronics. Despite its promising potential, the insufficient control over charge states and electronic stabilities must be overcome in molecular electronic devices. Here, we show the reversible switching of modulated charge states in an exfoliatable 2D-layered molecular conductor based on bis(ethylenedithio)tetrathiafulvalene molecular dimers. The multiple stimuli application of cooling rate, current, voltage, and laser irradiation in a concurrent manner facilitates the controllable manipulation of charge crystal, glass, liquid, and metal phases. The four orders of magnitude switching of electric resistance are triggered by stimuli-responsive charge distribution among molecular dimers. The tunable charge transport in 2D molecular conductors reveals the kinetic process of charge configurations under stimuli, promising to add electric functions in molecular circuitry.

Huang, Yulong (ORCID:0000000296160134)↗