Search NASA⌕ Search

SEARCH · Search NASA

Results for “Experiment Hardware”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Neutron Calibration Studies for the SuperCDMS SNOLAB Experiment

My time at Fermilab has been dedicated to advancing the field of dark matter detection through my contributions to the SuperCDMS collaboration. The first project involved the development and testing of a delivery system for a Cf-252 neutron source to calibrate the SuperCDMS silicon and germanium detectors. Subsequently, I focused on parametrizing the detectors' instrumental response by optimizing a plastic scintillator backing array to measure the scattering angle of a collimated neutron beam. The Monte Carlo simulation I designed provided insights into the detection efficiency of the array, and the best-fit design I arrived at for the scattering counters will be implemented into the final array. Additionally, I assembled a muon detector with legacy hardware to enhance the ability of the calibration experiment to reduce dark current and false signals. As my work nears completion, I am confident that these contributions will significantly enhance the precision and reliability of the SuperCDMS experiment, pushing the boundaries of our understanding of dark matter and contributing to the broader scientific community's quest to unravel the mysteries of the universe.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Approaches for Synthesis and Deployment of Controller Models on Automated Vehicles for Car-following in Mixed Autonomy

This paper describes the software design patterns and vehicle interfaces that were employed to transition vehicle controllers from simulation environments to open-road field experiments. The approach relies on a life cycle that utilizes model-based design and code generation, along with agile software development, and both software and hardware-in-the-loop testing, with additional safety margins. Autonomous designs should consider the dynamics of mixed autonomy in traffic to safely operate among humans. The software that provides a vehicle’s behavior intelligence is often developed through simulation, which may have a mismatch between dynamics, or as a result of a reinforcement learning workflow, which may be a black box with challenges to analyze. In each of these cases, it is important to have research interfaces that provide strongly typed data streams accessible to researchers who are not software experts while continuing to satisfy safety and liveness constraints. This paper describes how we design the hardware platform interfaces and software design process for a mixed autonomy traffic experiment with a leader-follower scenario. Controller synthesis for these vehicles requires clearly articulated vehicle interfaces and software design patterns for successful onboard deployment. Testing strategies for such controllers are also described before algorithms are transitioned to full-scale field experiments with safety operators for the vehicles. Testing strategies include software-in-the-loop simulation testing, hardware-in-the-loop simulation, ghost-car testing, and read-only testing in live traffic. With our approach, we were not only able to validate our controller synthesized in scripts and simulation, but also able to scale deployment to multiple vehicles.

Bhadani, Rahul↗
DOE OSTI2024

Mitigating the Effects of Au-Al Intermetallic Compounds Due to High-Temperature Processing of Surface-Electrode Ion Traps

Stringent physical requirements need to be met for the high-performing surface-electrode ion traps used in quantum computing and timekeeping. In particular, these traps must survive a high-temperature environment for vacuum chamber preparation and support high RF voltage on closely spaced electrodes. Due to the use of gold wire bonds on aluminum pads, intermetallic growth can lead to wire bond failure via breakage or high resistance, limiting the lifetime of a trap assembly to a single multiday bake at 200 ° C. Using traditional thick metal stacks to prevent intermetallic growth, however, can result in trap failure due to RF breakdown events. Through high-temperature experiments, we conclude that an ideal metal stack for ion traps is Ti/Pt/Au (20/100/250 nm), which allows for a cumulative bakeable time of roughly 86 days without compromising the trap voltage performance. This increase in the bakeable lifetime of ion traps will remove the need to discard otherwise functional ion traps when vacuum hardware is upgraded, which will greatly benefit ion trap experiments.

Haltli, Raymond A.↗
DOE OSTI2023

Functional Meta-Analysis of the Proteomic Responses of Arabidopsis Seedlings to the Spaceflight Environment Reveals Multi-Dimensional Sources of Variability across Spaceflight Experiments

The human quest for sustainable habitation of extraterrestrial environments necessitates a robust understanding of life’s adaptability to the unique conditions of spaceflight. This study provides a comprehensive proteomic dissection of the Arabidopsis plant’s responses to the spaceflight environment through a meta-analysis of proteomics data from four separate spaceflight experiments conducted on the International Space Station (ISS) in different hardware configurations. Raw proteomics LC/MS spectra were analyzed for differential expression in MaxQuant and Perseus software. The analysis of dissimilarities among the datasets reveals the multidimensional nature of plant proteomic responses to spaceflight, impacted by variables such as spaceflight hardware, seedling age, lighting conditions, and proteomic quantification techniques. By contrasting datasets that varied in light exposure, we elucidated proteins involved in photomorphogenesis and skotomorphogenesis in plant spaceflight responses. Additionally, with data from an onboard 1 g control experiment, we isolated proteins that specifically respond to the microgravity environment and those that respond to other spaceflight conditions. This study identified proteins and associated metabolic pathways that are consistently impacted across the datasets. Notably, these shared proteins were associated with critical metabolic functions, including carbon metabolism, glycolysis, gluconeogenesis, and amino acid biosynthesis, underscoring their potential significance in Arabidopsis’ spaceflight adaptation mechanisms and informing strategies for successful space farming.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

Looking in the axion mirror: An all-sky analysis of stimulated decay

Axion dark matter (DM) produces echo images of bright radio sources via stimulated decay. These images appear as a faint radio line centered at half the axion mass, with the line width set by the DM velocity dispersion. Due to the kinematics of the decay, the echo can be emitted in the direction nearly opposite to the incoming source of stimulating radiation, meaning that axions effectively behave as imperfect monochromatic mirrors. We present an all-sky analysis of axion DM-induced echo images using extragalactic radio point sources, Galactic supernova remnants (SNRs), and Galactic synchrotron radiation (GSR) as sources of stimulating radiation. The aggregate signal strength is not significantly affected by unknown properties of individual sources of stimulating radiation, which we sample from an empirical distribution to generate an ensemble of realizations for the all-sky signal template. We perform forecasts for CHIME, HERA, CHORD, HIRAX, and BURSTT, finding that they can run as competitive axion experiments simultaneously with other objectives, requiring no new hardware.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
DOE OSTI2026

Magnetic hysteresis experiments performed on quantum annealers

While quantum annealers have emerged as versatile and controllable platforms for experimenting on correlated spin systems, the important phenomenology of magnetic memory and hysteresis remain unexplored on hardware designed to escape metastable states via quantum tunneling. Here, we present the first general protocol to experiment on magnetic hysteresis on programmable quantum annealers and implement it on three D-Wave superconducting qubit quantum annealers, using up to thousands of spins, for both ferromagnetic and disordered Ising models, and across different graph topologies. We observe hysteresis loops whose area depends nonmonotonically on quantum fluctuations, exhibiting both expected and unexpected features, such as disorder-induced steps and nonmonotonicities. Our work establishes quantum annealers as a platform for probing nonequilibrium emergent magnetic phenomena, thereby broadening the role of analog quantum computers into foundational questions in condensed matter physics.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Development of Real-Time High-Density Pulsar Data Transmission and Processing for Grid Synchronization

Taking advantage of the extreme stability of the pulsar period, it can serve as the timing source for grid synchronization to compensate for the timing drift instigated by the loss of GPS signal. Nevertheless, the real-time transmission and processing of the pulsar data suffer from its high-frequency data rate, varying from megahertz to gigahertz, resulting in reduced computing speed and increased time delay. To mitigate this issue, the hardware and software frameworks are implemented for the high-density pulsar data transmission and processing for grid synchronization in this research. Initially, the high-density pulsar data is transferred using open-source software. The complementary duty cycle timing module is designed to coordinate the operation of the dual-channel high-speed interface and software. Subsequently, the multiple-threading is applied to the receiving, parsing, and splicing pulsar data. Next, the pulsar signal extraction method is implemented based on the polyphase filterbank and time of arrival estimation. Ultimately, real-time performance verification experiments are carried out for different components under two hardware platforms. Finally, the results demonstrate that only 0.482 s is required for processing 4 Gigabyte data through multiple-threading, which is 3.8 times faster than the single thread. The pulsar signal extraction can also be executed within 707 ms for 4.8 seconds of data, thereby indicating that real-time requirements can be met.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2026

Machine Learning on Heterogeneous, Edge, and Quantum Hardware for Particle Physics (ML-HEQUPP)

The next generation of particle physics experiments will face a new era of challenges in data acquisition, due to unprecedented data rates and volumes along with extreme environments and operational constraints. Harnessing this data for scientific discovery demands real-time inference and decision-making, intelligent data reduction, and efficient processing architectures beyond current capabilities. Crucial to the success of this experimental paradigm are several emerging technologies, such as artificial intelligence and machine learning (AI/ML) and silicon microelectronics, and the advent of quantum algorithms and processing. Their intersection includes areas of research such as low-power and low-latency devices for edge computing, heterogeneous accelerator systems, reconfigurable hardware, novel codesign and synthesis strategies, readout for cryogenic or high-radiation environments, and analog computing. This white paper presents a community-driven vision to identify and prioritize research and development opportunities in hardware-based ML systems and corresponding physics applications, contributing towards a successful transition to the new data frontier of fundamental science.

Gonski, Julia [SLAC]↗
DOE OSTI2024

Experiences with implementing Kokkos’ SYCL backend

With the recent diversification of the hardware landscape in the high-performance computing community, performance-portability solutions are becoming more and more important. One of the most popular choices is Kokkos. In this paper, we describe how Kokkos maps to SYCL 2020, how SYCL had to evolve to enable a full Kokkos implementation, and where we still rely on extensions provided by Intel’s oneAPI implementation. Furthermore, we describe how applications can use Kokkos and its ecosystem to already explore upcoming C++ features also when using the SYCL backend. Finally, we are providing some performance benchmarks comparing native SYCL and Kokkos and also discuss hierarchical parallelism in the SYCL 2020 interface.

Arndt, Daniel↗
DOE OSTI2023

Monitoring the readout temperature in the ICARUS TPC (2023 Italian Students Program Final Report)

Being a Liquid Argon Time Projection Chamber (LAr-TPC) detector, ICARUS exploits a series of three parallel wire planes to measure and collect the ionization charge coming from an event inside the active volume. The wires are read out by A2795 custom boards, arranged in crates located on top of the two liquid Argon vessels. Each board is provided with two temperature sensors that allow temperature monitoring while the experiment is running: this is key in order to ensure data reliability and maintain hardware in safe conditions. Moreover, temperature-related problems may force unplanned shutdowns that result in losing valuable time for the experiment to run. In this work we are discussing the characterization of the ICARUS TPC board temperatures and the system we implemented in order to monitor them effectively. Among the tools used, Grafana results in a valid application for both displaying temperature data and sending alerts to the shifters whenever a pathological situation occurs.

42 ENGINEERING↗
DOE OSTI2023

Software and Hardware Development for the Mu2e Trigger and Data Acquisition System

The Mu2e experiment at Fermilab will be 10,000 times more sensitive than previous experiments looking for muon-to-electron conversion. This precise and complex experimental apparatus will produce 200 million billion muons per year. The accelerator complex repurposes elements of the infrastructure that produced high energy proton and anti-protons beams for the Tevatron experiments to produce the high-intensity muon beams necessary for Mu2e and the Muon (g-2) experiments.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

GFM Inverter Hardware Testing

This presentence provides overview of NREL's testing capabilities and experience with advanced testing of multimegawatt grid-forming inverters.

GFM↗
DOE OSTI2021

Q-VR: System-Level Design for Future Mobile Collaborative Virtual Reality

High Quality Mobile Virtual Reality (VR) is what the incoming graphics technology era demands: users around the world, regardless of their hardware and network conditions, can all enjoy the immersive virtual experience. However, the state-of-the-art software-based mobile VR designs cannot fully satisfy the realtime performance requirements due to the highly interactive nature of user's actions and complex environmental constraints during VR execution. Inspired by the unique human visual system effects and the strong correlation between VR motion features and realtime hardware-level information, we propose Q-VR, a novel dynamic collaborative rendering solution via software-hardware co-design for enabling future low-latency high-quality mobile VR. At software-level, Q-VR provides flexible high-level tuning interface to reduce network latency while maintaining user perception. At hardware-level, Q-VR accommodates a wide spectrum of hardware and network conditions across users by effectively leveraging the computing capability of the increasingly powerful VR hardware. Extensive evaluation on real-world games demonstrates that Q-VR can achieve an average end-to-end performance speedup of 3.4x (up to 6.7x) over the traditional local rendering design in commercial VR devices, and a 4.1x frame rate improvement over the state-of-the-art static collaborative rendering.

Xie, Chenhao↗
DOE OSTI2026

Captan+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗
DOE OSTI2026

CAPTAN+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗
DOE OSTI2020

Characterizing Output Bottlenecks of a Production Supercomputer: Analysis and Implications

This article studies the I/O write behaviors of the Titan supercomputer and its Lustre parallel file stores under production load. The results can inform the design, deployment, and configuration of file systems along with the design of I/O software in the application, operating system, and adaptive I/O libraries.We propose a statistical benchmarking methodology to measure write performance across I/O configurations, hardware settings, and system conditions. Moreover, we introduce two relative measures to quantify the write-performance behaviors of hardware components under production load. In addition to designing experiments and benchmarking on Titan, we verify the experimental results on one real application and one real application I/O kernel, XGC and HACC IO, respectively. These two are representative and widely used to address the typical I/O behaviors of applications.In summary, we find that Titan’s I/O system is variable across the machine at fine time scales. This variability has two major implications. First, stragglers lessen the benefit of coupled I/O parallelism (striping). Peak median output bandwidths are obtained with parallel writes to many independent files, with no striping or write sharing of files across clients (compute nodes). I/O parallelism is most effective when the application—or its I/O libraries—distributes the I/O load so that each target stores files for multiple clients and each client writes files on multiple targets in a balanced way with minimal contention. Second, our results suggest that the potential benefit of dynamic adaptation is limited. In particular, it is not fruitful to attempt to identify “good locations” in the machine or in the file system: component performance is driven by transient load conditions and past performance is not a useful predictor of future performance. For example, we do not observe diurnal load patterns that are predictable.

97 MATHEMATICS AND COMPUTING↗