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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2017

Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments

SRAM-ba8ed Field Programmable Gate Array (FPGA) logic devices arc very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. :!\litigation techniques such as Triple Modular Redundancy (T:t\IR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2018

Characterisation and testing of CHEC-M—A camera prototype for the small-sized telescopes of the Cherenkov telescope array

The Compact High Energy Camera (CHEC) is a camera design for the Small-Sized Telescopes (SSTs; 4 m diameter mirror) of the Cherenkov Telescope Array (CTA). The SSTs are focused on very-high-energy γ-ray detection via atmospheric Cherenkov light detection over a very large area. This implies many individual units and hence cost-effective implementation, as well as shower detection at large impact distance, and hence large field of view (FoV), and efficient image capture in the presence of large time gradients in the shower image detected by the camera. CHEC relies on dual-mirror optics to reduce the plate-scale and make use of 6 x 6 mm 2 pixels, leading to a low-cost (~150 k€), compact (0.5 m x 0.5 m), and light (~45 kg) camera with 2048 pixels providing a camera FoV of ~9 degrees. The CHEC electronics are based on custom TARGET (TeV array readout with GSa/s sampling and event trigger) application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) sampling incoming signals at a gigasample per second, with flexible camera-level triggering within a single backplane FPGA. CHEC is designed to observe in the γ-ray energy range of 1–300 TeV, and at impact distances up to 500 m. To accommodate this and provide full flexibility for later data analysis, full waveforms with 96 samples for all 2048 pixels can be read out at rates up to ~900 Hz. The first prototype, CHEC-M, based on multi-anode photomultipliers (MAPMs) as photosensors, was commissioned and characterised in the laboratory and during two measurement campaigns on a telescope structure at the Paris Observatory in Meudon. Here in this paper, the results and conclusions from the laboratory and on-site testing of CHEC-M are presented. They have provided essential input on the system design and on operational and data analysis procedures for a camera of this type. In conclusion, a second full-camera prototype based on Silicon photomultipliers (SiPMs), addressing the drawbacks of CHEC-M identified during the first prototype phase, has already been built and is currently being commissioned and tested in the laboratory.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2018

KALYPSO: Linear array detector for high-repetition rate and real-time beam diagnostics

Synchrotrons and modern FEL light sources operate with bunch repetition rates in the MHz range. The profile of the electron beam inside the accelerator can be characterized with indirect experimental techniques where linear array detectors are employed to measure the emitted synchrotron radiation or the spectrum of a near-IR laser. To improve the performance of modern beam diagnostics we have developed KALYPSO, a detector system operating with a continuous frame rate of up to 2.7 MHz. To facilitate the integration in different experiments, a modular architecture has been adopted. Different semiconductor micro-strip sensors can be connected to front-end ASICs to optimize the quantum efficiency at different photon energies, ranging from visible light up to near-IR. The front-end electronics are integrated within an heterogeneous DAQ consisting of FPGAs and GPUs, which allows scientists to implement real-time data processing algorithms. The current version of the detector is in operation at the KARA synchrotron light source and at the European XFEL. Finally, in this contribution we present the detector architecture, the performance results and the on-going technical developments.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2019

Development and data path integration test of the global Feature EXtractor for the ATLAS Level-1 calorimeter trigger system Phase-I upgrade

The global Feature Extractor (gFEX) is a component of the Phase-I upgrade of the Level-1 Calorimeter (L1Calo) trigger system for the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. The gFEX is used to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W and Z bosons, top quarks, and exotic particles in real time at the 40 MHz LHC bunch crossing rate. Three prototypes were implemented and tested from 2014 to 2017. With the lessons learned from the prototypes, the final gFEX production board has been implemented at the end of 2017. The gFEX receives up to 300 fiber optical links from the calorimeter and transmits trigger data on 96 links to the ATLAS Level-1 Topological [1] (L1Topo) trigger at a rate of up to 12.8 Gb/s. There are also 24 electrical links on board for communication between two FPGAs running at speeds of up to 25.6 Gb/s. Here, the hardware functionality and performance of the production board have been evaluated. A data path integration test between the Liquid Argon Digital Processing Blade (LDPB) [2] and the Front End LInk eXchange (FELIX) [3] was performed successfully at CERN in 2018.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2019

A microbenchmark characterization of the Emu chick

The Emu Chick is a prototype system designed around the concept of migratory memory-side processing. Rather than transferring large amounts of data across power-hungry, high-latency interconnects, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each memory read. The current prototype hardware uses FPGAs to implement cache-less “Gossamer” cores for computational work and rely on a typical stationary core (PowerPC) to run basic operating system functions and migrate threads between nodes. In this multi-node characterization of the Emu Chick, we extend an earlier single-node investigation of the the memory bandwidth characteristics of the system through benchmarks like STREAM, pointer chasing, and sparse matrix-vector multiplication. Here, we compare the Emu Chick hardware to architectural simulation and an Intel Xeon-based platform. Our results demonstrate that for many basic operations the Emu Chick can use available memory bandwidth more efficiently than a more traditional, cache-based architecture although bandwidth usage suffers for computationally intensive workloads like SpMV. Moreover, the Emu Chick provides stable, predictable performance with up to 65% of the peak bandwidth utilization on a random-access pointer chasing benchmark with weak locality.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

ATLAS FTK Challenge: Simulation of a Billion-fold Hardware Parallelism

During the current LHC shutdown period the ATLAS experiment will upgrade the Trigger and Data Acquisition system to include a hardware tracker coprocessor: the Fast TracKer (FTK). The FTK receives data from the 80 million of channels of the ATLAS silicon detector, identifying charged tracks and reconstructing their parameters at a rate of up to 100 KHz and within 100 microseconds. To achieve this performance, the FTK system identifies candidate tracks utilizing the computing power of a custom ASIC chip with associative memory (AM) designed to perform “pattern matching” at very high speed; track parameters are then calculated using modern FPGAs. A detailed simulation of this massive system has been developed with the goal of supporting the hardware design and studying its impact in the ATLAS online event selection at high LHC luminosities. We present the issues related to emulating FTK on a general-purpose CPU platform, using ATLAS computing Grid resources, and the solutions developed in order to mitigate these problems and allow the studies required to support the system design, construction and installation.

Distributed Computing↗
DOE OSTI2022

Accelerators for Classical Molecular Dynamics Simulations of Biomolecules

Atomistic Molecular Dynamics (MD) simulations provide researchers the ability to model biomolecular structures such as proteins and their interactions with drug-like small molecules with greater spatiotemporal resolution than is otherwise possible using experimental methods. MD simulations are notoriously expensive computational endeavors that have traditionally required massive investment in specialized hardware to access biologically relevant spatiotemporal scales. Our goal is to summarize the fundamental algorithms that are employed in the literature to then highlight the challenges that have affected accelerator implementations in practice. We consider three broad categories of accelerators: Graphics Processing Units (GPUs), Field-Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuits (ASICs). These categories are comparatively studied to facilitate discussion of their relative trade-offs and to gain context for the current state of the art. We conclude by providing insights into the potential of emerging hardware platforms and algorithms for MD.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

HDBind: encoding of molecular structure with hyperdimensional binary representations

Traditional methods for identifying “hit” molecules from a large collection of potential drug-like candidates rely on biophysical theory to compute approximations to the Gibbs free energy of the binding interaction between the drug and its protein target. These approaches have a significant limitation in that they require exceptional computing capabilities for even relatively small collections of molecules. Increasingly large and complex state-of-the-art deep learning approaches have gained popularity with the promise to improve the productivity of drug design, notorious for its numerous failures. However, as deep learning models increase in their size and complexity, their acceleration at the hardware level becomes more challenging. Hyperdimensional Computing (HDC) has recently gained attention in the computer hardware community due to its algorithmic simplicity relative to deep learning approaches. The HDC learning paradigm, which represents data with high-dimension binary vectors, allows the use of low-precision binary vector arithmetic to create models of the data that can be learned without the need for the gradient-based optimization required in many conventional machine learning and deep learning methods. This algorithmic simplicity allows for acceleration in hardware that has been previously demonstrated in a range of application areas (computer vision, bioinformatics, mass spectrometery, remote sensing, edge devices, etc.). To the best of our knowledge, our work is the first to consider HDC for the task of fast and efficient screening of modern drug-like compound libraries. We also propose the first HDC graph-based encoding methods for molecular data, demonstrating consistent and substantial improvement over previous work. We compare our approaches to alternative approaches on the well-studied MoleculeNet dataset and the recently proposed LIT-PCBA dataset derived from high quality PubChem assays. We demonstrate our methods on multiple target hardware platforms, including Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs), showing at least an order of magnitude improvement in energy efficiency versus even our smallest neural network baseline model with a single hidden layer. Our work thus motivates further investigation into molecular representation learning to develop ultra-efficient pre-screening tools. We make our code publicly available at https://github.com/LLNL/hdbind.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2020

40 MHz Level-1 Trigger Scouting for CMS

The CMS experiment will be upgraded for operation at the HighLuminosity LHC to maintain and extend its physics performance under extreme pileup conditions. Upgrades will include an entirely new tracking system, supplemented by a track finder processor providing tracks at Level-1, as well as a high-granularity calorimeter in the endcap region. New front-end and back-end electronics will also provide the Level-1 trigger with high-resolution information from the barrel calorimeter and the muon systems. The upgraded Level-1 processors, based on powerful FPGAs, will be able to carry out sophisticated feature searches with resolutions often similar to the offline ones, while keeping pileup effects under control. In this paper, we discuss the feasibility of a system capturing Level-1 intermediate data at the beam-crossing rate of 40 MHz and carrying out online analyzes based on these limited-resolution data. This 40 MHz scouting system would provide fast and virtually unlimited statistics for detector diagnostics, alternative luminosity measurements and, in some cases, calibrations. It has the potential to enable the study of otherwise inaccessible signatures, either too common to fit in the Level-1 accept budget, or with requirements which are orthogonal to “mainstream” physics, such as long-lived particles. We discuss the requirements and possible architecture of a 40 MHz scouting system, as well as some of the physics potential, and results from a demonstrator operated at the end of Run-2 using the Global Muon Trigger data from CMS. Plans for further demonstrators envisaged for Run-3 are also discussed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Evaluating Performance Portability with the CMS Heterogeneous Pixel Reconstruction code

In the past years the landscape of tools for expressing parallel algorithms in a portable way across various compute accelerators has continued to evolve significantly. There are many technologies on the market that provide portability between CPU, GPUs from several vendors, and in some cases even FPGAs. These technologies include C++ libraries such as Alpaka and Kokkos, compiler directives such as OpenMP, the SYCL open specification that can be implemented as a library or in a compiler, and standard C++ where the compiler is solely responsible for the offloading. Given this developing landscape, users have to choose the technology that best fits their applications and constraints. For example, in the CMS experiment the experience so far in heterogeneous reconstruction algorithms suggests that the full application contains a large number of relatively short computational kernels and memory transfer operations. In this work we use a stand-alone version of the CMS heterogeneous pixel reconstruction code as a realistic use case of HEP reconstruction software that is capable of leveraging GPUs effectively. We summarize the experience of porting this code base from CUDA to Alpaka, Kokkos, SYCL, std::par, and OpenMP offloading. We compare the event processing throughput achieved by each version on NVIDIA and AMD GPUs as well as on a CPU, and compare those to what a native version of the code achieves on each platform.

Andriotis, Nikolaos↗
DOE OSTI2025

Evolution of the ATLAS event data model for the HL-LHC

The upcoming high-luminosity run of the CERN Large Hadron Collider (HL-LHC) will yield an unprecedented volume of data. In order to process this data, the ATLAS collaboration is evolving its offline software to be able to use heterogeneous resources such as graphical processing units (GPUs) and field-programmable gate arrays (FPGAs). To reduce conversion overheads, the event data model (EDM) should be compatible with the requirements of these resources. While the ATLAS EDM has long allowed representing data as a structure of arrays, further evolution of the EDM can enable more efficient sharing of data between CPU and GPU resources. Some of this work will be summarized here, including extensions to allow controlling how memory for event data is allocated and the implementation of jagged vectors.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2014

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2012

FPGA-based gating and logic for multichannel single photon counting

We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidence measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2018

The HEP.TrkX Project: Deep Learning for Particle Tracking

Charged particle reconstruction in dense environments, such as the detectors of the High Luminosity Large Hadron Collider (HL-LHC) is a challenging pattern recognition problem. Traditional tracking algorithms, such as the combinatorial Kalman Filter, have been used with great success in HEP experiments for years. However, these state-of-the-art techniques are inherently sequential and scale quadratically or worse with increased detector occupancy. The HEP.TrkX project is a pilot project with the aim to identify and develop cross-experiment solutions based on machine learning algorithms for track reconstruction. Machine learning algorithms bring a lot of potential to this problem thanks to their capability to model complex non-linear data dependencies, to learn effective representations of high-dimensional data through training, and to parallelize easily on high-throughput architectures such as FPGAs or GPUs. In this paper we present the evolution and performance of our recurrent (LSTM) and convolutional neural networks moving from basic 2D models to more complex models and the challenges of scaling up to realistic dimensionality/sparsity.

Tsaris, Aristeidis↗
DOE OSTI2012

Upgrade of the CMS hadron calorimeter for an upgraded LHC

The CMS barrel and endcap hadron calorimeters (Hcal) upgrading the current photo-sensors are hybrid photodiodes (HPDs) to meet the demands of the upgraded luminosity of the LHC. A key aspect of the Hcal upgrade is to add longitudinal segmentation to improve background rejection, energy resolution, and electron isolation at L1 trigger. The increased segmentation can be achieved by replacing the HPD's with multi-pixel Geiger-mode avalanche photodiodes. The upgraded electronics are required to operate in a harsh environment and are constrained by the existing infrastructure. The proposed solutions span from chip level to system level. They include the development of a new ADC ASIC, the design and testing of higher speed transmitters to handle the increased data volume, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design and improvements in the overall architecture.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2017

An Artificial Retina Processor for Track Reconstruction at the LHC Crossing Rate

The goal of the INFN-RETINA R&D project is to develop and implement a computational methodology that allows to reconstruct events with a large number (> 100) of charged-particle tracks in pixel and silicon strip detectors at 40 MHz, thus matching the requirements for processing LHC events at the full bunch-crossing frequency. Our approach relies on a parallel pattern-recognition algorithm, dubbed artificial retina, inspired by the early stages of image processing by the brain. In order to demonstrate that a track-processing system based on this algorithm is feasible, we built a sizable prototype of a tracking processor tuned to 3 000 patterns, based on already existing readout boards equipped with Altera Stratix III FPGAs. The detailed geometry and charged-particle activity of a large tracking detector currently in operation are used to assess its performances. We report on the test results with such a prototype.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

FPGA-based tracking for the CMS Level-1 trigger using the tracklet algorithm

The high instantaneous luminosities expected following the upgrade of the Large Hadron Collider (LHC) to the High-Luminosity LHC (HL-LHC) pose major experimental challenges for the CMS experiment. A central component to allow efficient operation under these conditions is the reconstruction of charged particle trajectories and their inclusion in the hardware based trigger system. There are many challenges involved in achieving this: a large input data rate of about 20–40 Tb/s; processing a new batch of input data every 25 ns, each consisting of about 15,000 precise position measurements and rough transverse momentum measurements of particles (“stubs”); performing the pattern recognition on these stubs to find the trajectories; and producing the list of trajectory parameters within 4 µs. Here, this paper describes a proposed solution to this problem, specifically, it presents a novel approach to pattern recognition and charged particle trajectory reconstruction using an all-FPGA solution. The results of an end-to-end demonstrator system, based on Xilinx Virtex-7 FPGAs, that meets timing and performance requirements are presented along with a further improved, optimized version of the algorithm together with its corresponding expected performance.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10 –15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

Instruments & Instrumentation↗