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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Silicon carbide semiconductor technology for high temperature and radiation environments

Viewgraphs on silicon carbide semiconductor technology and its potential for enabling electronic devices to function in high temperature and high radiation environments are presented. Topics covered include silicon carbide; sublimation growth of 6H-SiC boules; SiC chemical vapor deposition reaction system; 6H silicon carbide p-n junction diode; silicon carbide MOSFET; and silicon carbide JFET radiation response.

Matus, Lawrence G.↗
NASA NTRS1992

A broadband THz receiver for low background space applications

We have developed a sensitive bolometric receiver for low background space applications. In a 10 percent bandwidth at 1 THz, this receiver is approximately 100 times more sensitive than a quantum limited heterodyne receiver with a 1 GHz IF bandwidth. This receiver is designed to be used for the long wavelength band (200-700 microns) in the MIPS instrument on NASA's SIRTF satellite. The bolometers are cooled to 100 mK by an adiabatic demagnetization refrigerator. Roughly 60 g of cesium chrome alum salt is partially demagnetized to 100 mK, followed by a slow regulated downramp to compensate for the heat leak. The hold time of the ADR system is about 18 hours with a temperature stability of delta T(sub rms) approx. equals 10 micro-K. The composite bolometers have electrical responsivities of 10(exp 9)V/W and electrical NEP's of about 3x10(exp -17) W/square root of Hz. The bolometer signals are read out by JFET preamplifiers located on the helium plate and operated at 120 K. We have addressed a number of space qualification issues, such as the development of an analog magnet controller, construction of a cryogenic shake-table for bolometers and selection of the paramagnetic salt CCA which can survive a bakeout at 50 C. The receiver is scheduled to be flown in the spring of 1992 on a balloon telescope. This flight has a dual purpose. One is to provide realistic test of the capabilities of the new receiver. The other is to search for anisotropies in the cosmic microwave background on scales of a few degrees.

Hagmann, C.↗
NASA NTRS1992

Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

Fossum, Eric R.↗
NASA NTRS1995

The Yerkes Observatory 60-channel far infrared camera for the Kuiper Airborne Observatory

The Yerkes Observatory Far Infrared Camera employs a two-dimensional, 60-detector array of (3)He-cooled silicon bolometers for broadband imaging in the spectral range of 40 to 240 microns. Four interchangeable filters have effective wavelengths of 60, 100, 160, and 200 microns. Three interchangeable lens sets give pixel sizes of 17, 27, and 45 in. Signals are processed through nitrogen-temperature JFET source-follower amplifiers, warm preamplifiers, and digital signal processors, and the system is controlled through a graphical user interface on a Macintosh computer. The camera has been used to image a wide variety of galactic and extragalactic far infrared sources.

Harper, D. AL, Jr.↗
NASA NTRS1997

High Resolution X-Ray Spectroscopy Using Microcalorimeters

During the past 13 years high resolution X ray spectrometers have been developed that use cryogenically cooled microcalorimeters. These devices have inherently high signal-to-noise by operating at temperatures below 0.1 K and can achieve an energy resolution of < 10 eV over the 0.1-10 keV band. Existing devices use doped semiconductor thermometers and typically employ HgTe absorbers. The energy resolution depends on achieving a low heat capacity for the device. For soft X ray applications a relatively thin absorber (approximately 1 micrometer) may be used and an energy resolution of approximately 7 eV has been achieved. For applications up to approximately 10 keV an absorber thickness of approximately 10 micrometer is required and the energy resolution is typically approximately 12 eV. Improvements to the energy resolution in this energy band could be achieved if the problems of thermalizing X rays in low heat capacity superconductors can be overcome. The recent work on transition edge thermometers by Irwin et nl. looks particularly promising because of the higher sensitivity achievable from a sharp superconducting transition. The relatively low impedance of such a device permits the use of a low noise SQUID amplifier for readout. This would also significantly reduce the cryogen heat load compared with JFETs required by higher impedance semiconductor thermometers.

Kelley, R. L.↗
NASA NTRS2000

Characteristics of Monolithically Integrated InGaAs Active Pixel Imager Array

Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.

Kim, Q.↗
NASA NTRS2002

Design and Fabrication of Two-Dimensional Semiconducting Bolometer Arrays for the High Resolution Airborne Wideband Camera (HAWC) and the Submillimeter High Angular Resolution Camera II (SHARC-II)

The High resolution Airborne Wideband Camera (HAWC) and the Submillimeter High Angular Resolution Camera II (SHARC 11) will use almost identical versions of an ion-implanted silicon bolometer array developed at the National Aeronautics and Space Administration's Goddard Space Flight Center (GSFC). The GSFC "Pop-Up" Detectors (PUD's) use a unique folding technique to enable a 12 x 32-element close-packed array of bolometers with a filling factor greater than 95 percent. A kinematic Kevlar(Registered Trademark) suspension system isolates the 200 mK bolometers from the helium bath temperature, and GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The JFET preamps operate at 120 K. Providing good thermal heat sinking for these, and keeping their conduction and radiation from reaching the nearby bolometers, is one of the principal design challenges encountered. Another interesting challenge is the preparation of the silicon bolometers. They are manufactured in 32-element, planar rows using Micro Electro Mechanical Systems (MEMS) semiconductor etching techniques, and then cut and folded onto a ceramic bar. Optical alignment using specialized jigs ensures their uniformity and correct placement. The rows are then stacked to create the 12 x 32-element array. Engineering results from the first light run of SHARC II at the CalTech Submillimeter Observatory (CSO) are presented.

Voellmer, George M.↗
NASA NTRS2002

Design and Fabrication of Two-Dimensional Semiconducting Bolometer Arrays for the High Resolution Airborne Wideband Camera (HAWC) and the Submillimeter High Angular Resolution Camera II (SHARC-II)

The High resolution Airborne Wideband Camera (HAWC) and the Submillimeter High Angular Resolution Camera II (SHARC II) will use almost identical versions of an ion-implanted silicon bolometer array developed at the National Aeronautics and Space Administration's Goddard Space Flight Center (GSFC). The GSFC 'Pop-up' Detectors (PUD's) use a unique folding technique to enable a 12 x 32-element close-packed array of bolometers with a filling factor greater than 95 percent. A kinematic Kevlar(trademark) suspension system isolates the 200 mK bolometers from the helium bath temperature, and GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The JFET preamps operate at 120 K. Providing good thermal heat sinking for these, and keeping their conduction and radiation from reaching the nearby bolometers, is one of the principal design challenges encountered. Another interesting challenge is the preparation of the silicon bolometers. They are manufactured in 32-element, planar rows using Micro Electro Mechanical Systems (MEMS) semiconductor etching techniques, and then cut and folded onto a ceramic bar. Optical alignment using specialized jigs ensures their uniformity and correct placement. The rows are then stacked to create the 12 x 32-element array. Engineering results from the first light run of SHARC II at the Caltech Submillimeter Observatory (CSO) are presented.

Voellmer, George M.↗
NASA NTRS2000

NTD-GE Based Microcalorimeter Performance

Our group has been developing x-ray microcalorimeters consisting of neutron transmutation doped (NTD) germanium thermistors attached to superconducting tin absorbers. We discuss the performance of single pixel x-ray detectors, and describe an array technology. In this paper we describe the read-out circuit that allows us to measure fast signals in our detectors as this will be important in understanding the primary cause of resolution broadening. We describe briefly a multiplexing scheme that allows a number of different calorimeters to be read out using a single JFET. We list the possible causes of broadening and give a description of the experiment which best demonstrates the cause of the primary broadening source. We mention our strategy for finding a suitable solution to this problem and describe briefly a technology for building arrays of these calorimeters.

Bandler, Simon↗
NASA NTRS2003

Development of a Cryogen-Free Continuous ADR for the Constellation-X Mission

Constellation-X is a multi-satellite x-ray astronomy mission presently being planned for launch in the 2010 time frame. Each of 4 identical satellites will contain a telescope and instruments for imaging and spectroscopic analysis of both hard and soft x-rays. The X- ray Microcalorimeter Spectrometer (XMS) instrument will use arrays of microcalorimeters to detect X-rays with energies from 0.2 to 6 keV. The technologies under development for this instrument include Transition-Edge Sensors (TES) with multiplexed SQUID readouts and NTD-Ge detectors with JFET readouts. Both will be operated at temperatures in the 50-60 mK range and both have a projected cooling power requirement of approximately 5 microwatts. In addition, in order to meet the lifetime requirement of 6 years (with a goal of 10 years), a mechanical cryocooler will be used to provide a heat sink for the low temperature cooler. The required performance is 20 mW at 6 K, with a goal of 4 K operation. In this paper we present the development status of an adiabatic demagnetization refigerator (ADR) that meets the cooling requirements of the X M S instrument. At present we have demonstrated a 4-stage ADR that operates continuously at 50 mK using a 4.2 K helium bath as a heat sink. The cooling power is 21 microwatts at 100 mK and 6 microwatts at 50 mK. Its efficiency when operating at 50 mK is 1 1 % of Carnot (accounting for all dissipation at 4.2 K and below, but not including power dissipation in the room temperature electronics), but this is expected to rise to 25% in the next generation system in which active gas-gap heat switches are replaced with passive devices. This will reduce the peak heat rejection rate of the ADR to less than 7 mW at 6 K. Details of the ADR s design and operation, as well as the development program leading up to a flight-qualified instrument, will be discussed.

Shirron, Peter↗
NASA NTRS2002

The four-gate transistor

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

neuro-prosthetic devices cortical signals↗
NASA NTRS1997

GaAs Multiplexers for VLWIR Detector Readout Below 10 Kelvin

A multiplexer and buffer based on GaAs JFET technology is presented. This multiplexer operates normally from room temperature down to 4 Kelvin and is suitable for the readout of Very Long Wavelength Infrared Detectors that must be cooled to below 10 Kelvin.

detector arrays GaAs multiplexers↗
NASA NTRS2007

An Overview of Wide Bandgap Silicon Carbide Sensors and Electronics Development at NASA Glenn Research Center

A brief overview is presented of the sensors and electronics development work ongoing at NASA Glenn Research Center which is intended to meet the needs of future aerospace applications. Three major technology areas are discussed: 1) high temperature SiC electronics, 2) SiC gas sensor technology development, and 3) packaging of harsh environment devices. Highlights of this work include world-record operation of SiC electronic devices including 500?C JFET transistor operation with excellent properties, atomically flat SiC gas sensors integrated with an on-chip temperature detector/heater, and operation of a packaged AC amplifier. A description of the state-of-the-art is given for each topic. It is concluded that significant progress has been made and that given recent advancements the development of high temperature smart sensors is envisioned.

Hunter, Gary W.↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2011

NASA Tech Briefs, April 2011

Topics covered include: Amperometric Solid Electrolyte Oxygen Microsensors with Easy Batch Fabrication; Two-Axis Direct Fluid Shear Stress Sensor for Aerodynamic Applications; Target Assembly to Check Boresight Alignment of Active Sensors; Virtual Sensor Test Instrumentation; Evaluation of the Reflection Coefficient of Microstrip Elements for Reflectarray Antennas; Miniaturized Ka-Band Dual-Channel Radar; Continuous-Integration Laser Energy Lidar Monitor; Miniaturized Airborne Imaging Central Server System; Radiation-Tolerant, SpaceWire-Compatible Switching Fabric; Small Microprocessor for ASIC or FPGA Implementation; Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters; High-Voltage-Input Level Translator Using Standard CMOS; Monitoring Digital Closed-Loop Feedback Systems; MASCOT - MATLAB Stability and Control Toolbox; MIRO Continuum Calibration for Asteroid Mode; GOATS Image Projection Component; Coded Modulation in C and MATLAB; Low-Dead-Volume Inlet for Vacuum Chamber; Thermal Control Method for High-Current Wire Bundles by Injecting a Thermally Conductive Filler; Method for Selective Cleaning of Mold Release from Composite Honeycomb Surfaces; Infrared-Bolometer Arrays with Reflective Backshorts; Commercialization of LARC (trade mark) -SI Polyimide Technology; Novel Low-Density Ablators Containing Hyperbranched Poly(azomethine)s; Carbon Nanotubes on Titanium Substrates for Stray Light Suppression; Monolithic, High-Speed Fiber-Optic Switching Array for Lidar; Grid-Tied Photovoltaic Power System; Spectroelectrochemical Instrument Measures TOC; A Miniaturized Video System for Monitoring Drosophila Behavior; Hydrofocusing Bioreactor Produces Anti-Cancer Alkaloids; Creep Measurement Video Extensometer; Radius of Curvature Measurement of Large Optics Using Interferometry and Laser Tracker n-B-pi-p Superlattice Infrared Detector; Safe Onboard Guidance and Control Under Probabilistic Uncertainty; General Tool for Evaluating High-Contrast Coronagraphic Telescope Performance Error Budgets; Hidden Statistics of Schroedinger Equation; Optimal Padding for the Two-Dimensional Fast Fourier Transform; Spatial Query for Planetary Data; Higher Order Mode Coupling in Feed Waveguide of a Planar Slot Array Antenna; Evolutionary Computational Methods for Identifying Emergent Behavior in Autonomous Systems; Sampling Theorem in Terms of the Bandwidth and Sampling Interval; Meteoroid/Orbital Debris Shield Engineering Development Practice and Procedure; Self-Balancing, Optical-Center-Pivot, Fast-Steering Mirror; Wireless Orbiter Hang-Angle Inclinometer System; and Internal Electrostatic Discharge Monitor - IESDM.

Source record↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗