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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Method and apparatus for evaluating superconducting tunnel junction detector noise versus bias voltage

A technique for characterizing the noise behavior of a superconducting tunnel junction (STJ) detector as a function of its applied bias voltage Vb by stepping the STJ's bias voltage across a predetermined range and, at each applied bias, making multiple measurements of the detector's current, calculating their mean and their standard deviation from their mean, and using this standard deviation as a measure of the STJ detector's noise at that applied bias. Because the method is readily executed under computer control, it is particularly useful when large numbers of STJ detectors require biasing, as in STJ detector arrays In a preferred implementation, the STJ is measured under computer control by attaching it to a digital spectrometer comprising a digital x-ray processor (DXP) coupled to a preamplifier that can set the STJ's bias voltage Vb using a digital-to-analog converter (DAC) controlled by the DXP.

Warburton, William K.↗
DOE OSTI2020

Improving MPI Collective I/O for High Volume Non-Contiguous Requests With Intra-Node Aggregation

Two-phase I/O is a well-known strategy for implementing collective MPI-IO functions. It redistributes I/O requests among the calling processes into a form that minimizes the file access costs. As modern parallel computers continue to grow into the exascale era, the communication cost of such request redistribution can quickly overwhelm collective I/O performance. In this study, this effect has been observed from parallel jobs that run on multiple compute nodes with a high count of MPI processes on each node. Furthermore, to reduce the communication cost, we present a new design for collective I/O by adding an extra communication layer that performs request aggregation among processes within the same compute nodes. This approach can significantly reduce inter-node communication contention when redistributing the I/O requests. We evaluate the performance and compare it with the original two-phase I/O on Cray XC40 parallel computers (Theta and Cori) with Intel KNL and Haswell processors. Using I/O patterns from two large-scale production applications and an I/O benchmark, we show our proposed method effectively reduces the communication cost and hence maintains the scalability for a large number of processes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Modeling UV Radiation Feedback from Massive Stars. I. Implementation of Adaptive Ray-tracing Method and Tests [Modeling UV Radiation Feedback from Massive Stars: I. Implementation of Adaptive Ray Tracing Algorithm]

Here, we present an implementation of an adaptive ray-tracing (ART) module in the Athena hydrodynamics code that accurately and efficiently handles the radiative transfer involving multiple point sources on a three-dimensional Cartesian grid. We adopt a recently proposed parallel algorithm that uses nonblocking, asynchronous MPI communications to accelerate transport of rays across the computational domain. We validate our implementation through several standard test problems, including the propagation of radiation in vacuum and the expansions of various types of H II regions. Additionally, scaling tests show that the cost of a full ray trace per source remains comparable to that of the hydrodynamics update on up to $\sim {10}^{3}$ processors. To demonstrate application of our ART implementation, we perform a simulation of star cluster formation in a marginally bound, turbulent cloud, finding that its star formation efficiency is 12% when both radiation pressure forces and photoionization by UV radiation are treated. We directly compare the radiation forces computed from the ART scheme with those from the M 1 closure relation. Although the ART and M 1 schemes yield similar results on large scales, the latter is unable to resolve the radiation field accurately near individual point sources.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2023

Recent advances in describing and driving crystal nucleation using machine learning and artificial intelligence

With the advent of faster computer processors and especially graphics processing units (GPUs) over the last few decades, the use of data-intensive machine learning (ML) and artificial intelligence (AI) has increased greatly, and the study of crystal nucleation has been one of the beneficiaries. In this study, we outline how ML and AI have been applied to address four outstanding difficulties of crystal nucleation: how to discover better reaction coordinates (RCs) for describing accurately non-classical nucleation situations; the development of more accurate force fields for describing the nucleation of multiple polymorphs or phases for a single system; more robust identification methods for determining crystal phases and structures; and as a method to yield improved course-grained models for studying nucleation.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2019

CTF 4.0 User's Manual

The deck version is specified using the PPV flag on Card 1.1. In general, you should always use the latest version of the CTF input deck in order to make sure your model is treated correctly in CTF. This feature was added to retain backwards compatibility for older input decks. When an input deck is created with the CTF pre-processor, the latest version will always be used. Table 1 provides the revision history of the CTF input deck. The first column gives the version number of the deck and the second columns gives a description of what changed since the previous version of the input deck. This document describes how to make a CTF input deck. A CTF input deck is organized into Card Groups and Cards. A Card Group is a collection of Cards. A Card is defined as a line of input. Each Card may contain multiple data. A Card is terminated by making a new line. This document has been organized so that each Card Group is discussed in its own dedicated chapter. Each card is discussed in its own dedicated section. Each data in the card is discussed in its own block. The block gives information about the data, including the number of the input, the title, a description of the meaning of the data, units, data type, and so on. An example block is shown below to discuss the meaning of each entry in the block.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC

Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Although the majority of research focuses on measuring cache hit rates and data movement as the primary cache performance metrics, cache utilization is significantly important. We investigate the application’s locality using cache utilization metrics. In addition, we present cache utilization and traditional cache performance metrics as the program progresses providing detailed insights into the dynamic application behavior on parallel applications from four benchmark suites running on multiple cores. We explore cache utilization for APEX, Mantevo, NAS, and PARSEC, mostly scientific benchmark suites. Our results indicate that 40% of the data bytes in a cache line are accessed at least once before line eviction. Also, on average a byte is accessed two times before the cache line is evicted for these applications. Moreover, we present runtime cache utilization, as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. To facilitate this research, we build a memory simulator incorporated into the Structural Simulation Toolkit (Rodrigues et al. in SIGMETRICS Perform Eval Rev 38(4):37–42, 2011). Finally, our results suggest that variable cache line size can result in better performance and can also conserve power.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Numerical gate synthesis for quantum heuristics on bosonic quantum processors

There is a recent surge of interest and insights regarding the interplay of quantum optimal control and variational quantum algorithms. We study the framework in the context of qudits which are, for instance, definable as controllable electromagnetic modes of a superconducting cavity system coupled to a transmon. By employing recent quantum optimal control approaches described in (Petersson and Garcia, 2021), we showcase control of single-qudit operations up to eight states, and two-qutrit operations, mapped respectively onto a single mode and two modes of the resonator. We discuss the results of numerical pulse engineering on the closed system for parametrized gates useful to implement Quantum Approximate Optimization Algorithm (QAOA) for qudits. The results show that high fidelity ( > 0.99) is achievable with sufficient computational effort for most cases under study, and extensions to multiple modes and open, noisy systems are possible. The tailored pulses can be stored and used as calibrated primitives for a future compiler in circuit quantum electrodynamics (cQED) systems.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Refactoring the elastic–viscous–plastic solver from the sea ice model CICE v6.5.1 for improved performance

This study focuses on the performance of the elastic–viscous–plastic (EVP) dynamical solver within the sea ice model, CICE v6.5.1. The study has been conducted in two steps. First, the standard EVP solver was extracted from CICE for experiments with refactored versions, which are used for performance testing. Second, one refactored version was integrated and tested in the full CICE model to demonstrate that the new algorithms do not significantly impact the physical results. The study reveals two dominant bottlenecks, namely (1) the number of Message Parsing Interface (MPI) and Open Multi-Processing (OpenMP) synchronization points required for halo exchanges during each time step combined with the irregular domain of active sea ice points and (2) the lack of single-instruction, multiple-data (SIMD) code generation. The standard EVP solver has been refactored based on two generic patterns. The first pattern exposes how general finite differences on masked multi-dimensional arrays can be expressed in order to produce significantly better code generation by changing the memory access pattern from random access to direct access. The second pattern takes an alternative approach to handle static grid properties. The measured single-core performance improvement is more than a factor of 5 compared to the standard implementation. The refactored implementation of strong scales on the Intel® Xeon® Scalable Processors series node until the available bandwidth of the node is used. For the Intel® Xeon® CPU Max series, there is sufficient bandwidth to allow the strong scaling to continue for all the cores on the node, resulting in a single-node improvement factor of 35 over the standard implementation. This study also demonstrates improved performance on GPU processors.

58 GEOSCIENCES↗
DOE OSTI2024

Parallel hybrid quantum-classical machine learning for kernelized time-series classification

Supervised time-series classification garners widespread interest because of its applicability throughout a broad application domain including finance, astronomy, biosensors, and many others. Here, in this work, we tackle this problem with hybrid quantum-classical machine learning, deducing pairwise temporal relationships between time-series instances using a timeseries Hamiltonian kernel (TSHK). A TSHK is constructed with a sum of inner products generated by quantum states evolved using a parameterized time evolution operator. This sum is then optimally weighted using techniques derived from multiple kernel learning. Because we treat the kernel weighting step as a differentiable convex optimization problem, our method can be regarded as an end-to-end learnable hybrid quantum-classical-convex neural network, or QCC-net, whose output is a data set-generalized kernel function suitable for use in any kernelized machine learning technique such as the support vector machine (SVM). Using our TSHK as input to a SVM, we classify univariate and multivariate time-series using quantum circuit simulators and demonstrate the efficient parallel deployment of the algorithm to 127-qubit superconducting quantum processors using quantum multi-programming.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

ML–Enabled FPGA Framework for Fast Quantum State Discrimination in Mid-Circuit Measurement Regimes

Accurate and low-latency quantum state discrimination is essential for protocols involving mid-circuit measurement (MCM) and conditional feed-forward. In superconducting quantum systems, conventional readout pipelines transfer measurement data to host processors for post-processing, introducing millisecond-scale delays that far exceed qubit coherence times. To overcome this bottleneck, we present an in-situ machine learning (ML) inference engine implemented on an FPGA for real-time quantum state discrimination. Our design performs inference directly on digitized readout signals with 40 ns latency, supports both qubit and qutrit readout, and enables conditional operations without host-side intervention. This capability is critical for MCM and for feedback-driven protocols such as quantum error correction. We validate the system on superconducting transmon hardware, demonstrating robust discrimination fidelity across multiple qubit and qutrit channels. We further demonstrate conditional qutrit logic driven by FPGA-resident classification, highlighting the potential of low-latency ML-on-FPGA control for NISQ applications and scalable fault-tolerant quantum computing.

Vora, Neel [Lawrence Berkeley National Laboratory ↗
DOE OSTI2021

EMPIRE-PIC: A Performance Portable Unstructured Particle-in-Cell Code

In this study we introduce EMPIRE-PIC, a finite element method particle-in-cell (FEM-PIC) application developed at Sandia National Laboratories. The code has been developed in C++ using the Trilinos library and the Kokkos Performance Portability Framework to enable running on multiple modern compute architectures while only requiring maintenance of a single codebase. EMPIRE-PIC is capable of solving both electrostatic and electromagnetic problems in two- and three-dimensions to second-order accuracy in space and time. In this paper we validate the code against three benchmark problems — a simple electron orbit, an electrostatic Langmuir wave, and a transverse electromagnetic wave propagating through a plasma. We demonstrate the performance of EMPIRE-PIC on four different architectures: Intel Haswell CPUs, Intel's Xeon Phi Knights Landing, ARM Thunder-X2 CPUs, and NVIDIA Tesla V100 GPUs attached to IBM POWER9 processors. This analysis demonstrates scalability of the code up to more than two thousand GPUs, and greater than one hundred thousand CPUs.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

MODAL FREQUENCY TRACKING: Performance Analysis on Noisy Experimental Ground Test Data

Mechanical devices operating in an environment contaminated by noise, uncertainties, and extraneous disturbances lead to low signal-to-noise-ratios creating an extremely challenging signal processing problem—especially for on-line, realtime, in-flight application. In this report, we discuss a model-based approach to incorporate physical device features into a dynamic structure that can be used to perform on-line tracking of modal frequencies. The approach we take, after pre-processing the raw measurement data, is to obtain a representation of the structural device under test that captures its underlying response to a suite of excitations and operating conditions. One approach is to apply modern system identification techniques based on stochastic subspace methods capable of both: (1) identifying the underlying black-box structure enabling the extraction of structural modes that can be used for analysis; and (2) modal tracking under continued vibrational excitation as in a real-time, in-flight like environment. The vibrational signature of the structural device is measured directly using a suite of tri-axial accelerometers characterizing a multiple input/multiple output (MIMO) dynamic system. In this analysis, we have 15 tri-axial accelerometer measurements or 45 total output channels along with a single excitation also measured with a tri-axial accelerometer providing a 3-input system for processing. We initially describe the experiment and then briefly develop the necessary background in stochastic subspace realization, discuss the algorithm and apply it to the isolated structural device, first, characterized by the set of noisy MIMO accelerometer measurements extracting the modal model from the data (subspace identification), extract the unique modal frequencies (modal coordinate transformation), track their evolution (real-time tracker) to evaluate the overall performance of the processor. Next we evaluate processor performance when the structural device is incorporated into a flight vehicle for further performance analysis. We summarize the results and predict performance.

42 ENGINEERING↗
DOE OSTI2024

Mode-multiplexed photonic integrated vector dot-product core from inverse design

Photonic computing has the potential to harness the full degrees of freedom (DOFs) of the light field, including the wavelength, spatial mode, spatial location, phase quadrature, and polarization, to achieve a higher level of computing parallelism and scalability than digital electronic processors. While multiplexing using the wavelength and other DOFs can be readily integrated on silicon photonics platforms with compact footprints, conventional mode-division multiplexed (MDM) photonic designs occupy areas exceeding tens to hundreds of microns for a few spatial modes, significantly limiting their scalability. Here, we utilize inverse design to demonstrate an ultracompact photonic computing core that calculates vector dot products based on MDM coherent mixing. Our dot-product core integrates the functionalities of two-mode multiplexers and one multimode coherent mixer within a nominal footprint of 5 μm x 3 μm . We have experimentally demonstrated computing examples on the fabricated dot-product core, including complex number multiplication and motion estimation using optical flow. The compact dot-product core design enables large-scale on-chip integration in a parallel photonic computing primitive cluster for high-throughput scientific computing and computer vision tasks.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Certified randomness using a trapped-ion quantum processor

Although quantum computers can perform a wide range of practically important tasks beyond the abilities of classical computers, realizing this potential remains a challenge. An example is to use an untrusted remote device to generate random bits that can be certified to contain a certain amount of entropy. Certified randomness has many applications but is impossible to achieve solely by classical computation. Here we demonstrate the generation of certifiably random bits using the 56-qubit Quantinuum H2-1 trapped-ion quantum computer accessed over the Internet. Our protocol leverages the classical hardness of recent random circuit sampling demonstrations: a client generates quantum ‘challenge’ circuits using a small randomness seed, sends them to an untrusted quantum server to execute and verifies the results of the server. We analyse the security of our protocol against a restricted class of realistic near-term adversaries. Using classical verification with measured combined sustained performance of 1.1 × 10 18 floating-point operations per second across multiple supercomputers, we certify 71,313 bits of entropy under this restricted adversary and additional assumptions. Our results demonstrate a step towards the practical applicability of present-day quantum computers.

computer science↗
DOE OSTI2021

Development of MCNP Training Modules for Safeguards Practitioners [Abstract]

The Monte-Carlo N-Particle (MCNP) software developed at LANL is the most widely used neutron transport code in the world. It is an essential tool for a variety of applications including detector development and design, nuclear fuel burnup simulation, criticality safety, and nondestructive assay system optimization. For this reason, it is indispensable within the safeguards and materials control & accountability (MC&A) communities. Multiple MCNP training courses have been created and taught over the last several decades by the MCNP development team at LANL, however there are no existing courses that cover specialized topics considered fundamental to NDA and safeguards models. To fill this gap, the MCNP team and Safeguards Science and Technology group at LANL have co-created a set of training modules customized to meet the specialized needs of the safeguards and MC&A communities. The basic modules cover concepts such as NDA system optimization, He-specific and other capture tallies, and tools for improved theoretical understanding. An advanced module was also created to cover topics including variance reduction for active interrogation simulations, use of the LANL MCNPTools post-processor, PTRAC (particle tracking) and list-mode data simulations, and fuel burnup simulations. The training modules teach to the latest and most state-of-the-art MCNP features and tools released by the development team at LANL and are intended to be taught jointly by the developers and safeguards experts. Ultimately, we hope that creation of these modules will serve to capture and convey the safeguards modeling and MCNP expertise at LANL, and that we will be able to share the modules more broadly with the MC&A and safeguards communities.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2021

Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors

Hardware platforms in high performance computing are constantly getting more complex to handle even when considering multicore CPUs alone. Numerous features and configuration options in the hardware and the software environment that are relevant for performance are not even known to most application users or developers. Microbenchmarks, i.e., simple codes that fathom a particular aspect of the hardware, can help to shed light on such issues, but only if they are well understood and if the results can be reconciled with known facts or performance models. The insight gained from microbenchmarks may then be applied to real applications for performance analysis or optimization. In this paper we investigate two modern Intel x86 server CPU architectures in depth: Broadwell EP and Cascade Lake SP. We highlight relevant hardware configuration settings that can have a decisive impact on code performance and show how to properly measure on-chip and off-chip data transfer bandwidths. The new victim L3 cache of Cascade Lake and its advanced replacement policy receive due attention. Finally we use DGEMM, sparse matrix-vector multiplication, and the HPCG benchmark to make a connection to relevant application scenarios.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Accelerating Binarized Neural Networks via Bit-Tensor-Cores in Turing GPUs

Despite foreseeing tremendous speedups over conventional deep neural networks, the performance advantage of binarized neural networks (BNNs) has merely been showcased on general-purpose processors such as CPUs and GPUs. In fact, due to being unable to leverage bit-level-parallelism with a word-based architecture, GPUs have been criticized for extremely low utilization (1%) when executing BNNs. Consequently, the latest tensorcores in NVIDIA Turing GPUs start to experimentally support bit computation. In this work, we look into this brand new bit computation capability and characterize its unique features. We show that the stride of memory access can significantly affect performance delivery and a data-format co-design is highly desired to support the tensorcores for achieving superior performance than existing software solutions without tensorcores. We realize the tensorcore-accelerated BNN design, particularly the major functions for fully-connect and convolution layers — bit matrix multiplication and bit convolution. Evaluations on two NVIDIA Turing GPUs show that, with ResNet-18, our BTC-BNN design can process ImageNet at a rate of 5.6K images per second, 77% faster than state-of-the-art. Our BNN approach is released on https://github.com/pnnl/TCBNN.

Li, Ang↗
DOE OSTI2019

Improving efficiency of semi‐direct møller–plesset second‐order perturbation methods through oversubscription on multiple nodes

The purpose of this work is to evaluate the efficacy of oversubscription, at the 1 n , 2 n , and 3 n levels for n physical cores, on semi‐direct MP2 methods within NWChem when using two and three Intel nodes. Semi‐direct MP2 energy and gradient calculations were performed on chemical systems ranging from 824 to 1626 basis functions using the cc‐pVDZ basis set. Wall times for semi‐direct MP2 energies were reduced by as much as 36% using two nodes and 44% using three nodes compared to no oversubscription. Total energy consumed by the CPU and DRAM was also reduced by as much as 12% using two nodes and as much as 20% using three nodes when oversubscribing. MP2 gradient wall times improved by as much as 16% using two nodes and 18% using three nodes compared to execution at the 1 n level; however, energy savings were insignificant. Intel performance‐counter data show a strong correlation between total wall time saved and less time spent in the idle state, indicating a more efficient use of the processors when oversubscribing. © 2019 Wiley Periodicals, Inc.

Fought, Ellie L.↗