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A new family of semiconductor switches using double injection techniques and compensated deep impurities is described. They have the potential to raise switching voltages a factor of 10 higher (up to 100 kV) than p-n junction devices while exhibiting extremely low (or zero) forward voltage. Several potential power switching applications are indicated.
The microstructure of as-grown and processed, edge-defined film-fed grown, silicon ribbons was studied in order to identify the basic mechanisms responsible for the change of the as-grown defect structure during processing at elevated temperatures. The short heat treatment required to diffuse the p-n junction was sufficient to cause heterogeneous precipitation of impurity atoms, particularly transition metals. In addition, an elastic recovery of the ribbon occurred by dislocation glide, resulting in the formation of a polygonizationlike structure of subboundaries in the base. Mechanisms are suggested by which twin boundaries, acting as dislocation obstacles, can concentrate the relatively low average dislocation densities typical of edge-defined film-fed grown ribbons (10 to the 4th to 10 to the 8th/sq cm) to values which are sufficient to induce the formation of subgrainlike boundary structures.
Forward-bias tunneling is observed in heavily doped p-n junctions of bipolar transistors. A simple phenomenological model suitable to incorporation in device codes is developed. The model identifies as key parameters the space-charge-region (SCR) thickness at zero bias and the reduced doping level at its edges which can both be obtained from CV characteristics. This tunneling mechanism may limit the maximum gain achievable from scaled bipolar devices.
A new class of silicon devices operating without p-n junctions has been studied for radiation hardness. The electric field in these devices is uniform over most of the device, thus causing high-voltage breakdown to increase with electrode spacing. Deep acceptor levels are created in the silicon by diffusing gold atoms into the lattice, or by electron radiation. These acceptor levels, near the center of the band gap, trap out electrons so that the low resistivity of the n-type doped wafer can be raised to intrinsic resistivity. Switching between a high-resistivity state at low currents and a low-resistivity state at high currents occurs at a definite threshold voltage, exhibiting characteristics similar to silicon-controlled rectifiers. Compensating 0.1 ohm-meter (10 ohm-cm) silicon wafers requires electron fluxes of 10 to the 23rd electrons per square meter (10 to the 19th electrons per square centimeter). Experiments demonstrating gamma tolerance to 1 Gigarad(Si) are described. Calculations for maximum tolerable neutron fluence are shown, and a phenomenological explanation for these results is presented.
Computer-controlled ink-jet-assisted metallization of the front surface of solar cells with metalorganic silver inks offers a maskless alternative method to conventional photolithography and screen printing. This method can provide low cost, fine resolution, reduced process complexity, avoidance of degradation of the p-n junction by firing at lower temperature, and uniform line film on rough surface of solar cells. The metallization process involves belt furnace firing and thermal spiking. With multilayer ink jet printing and firing, solar cells of about 5-6 percent efficiency without antireflection (AR) coating can be produced. With a titanium thin-film underlayer as an adhesion promoter, solar cells of average efficiency 8.08 percent without AR coating can be obtained. This efficiency value is approximately equal to that of thin-film solar cells of the same lot. Problems with regard to lower inorganic content of the inks and contact resistance are noted.
A technique for fabricating a semiconductor heterostructure by growth of a ternary semiconductor on a binary semiconductor substrate from a melt of the ternary semiconductor containing less than saturation of at least one common ingredient of both the binary and ternary semiconductors wherein in a single temperature step the binary semiconductor substrate is etched, a p-n junction with specific device characteristics is produced in the binary semiconductor substrate by diffusion of a dopant from the melt and a region of the ternary semiconductor of precise conductivity type and thickness is grown by virtue of a change in the melt characteristics when the etched binary semiconductor enters the melt.
A technique for fabricating a semiconductor heterostructure by growth of a ternary semiconductor on a binary semiconductor substrate from a melt of the ternary semiconductor containing less than saturation of at least one common ingredient of both the binary and ternary semiconductors wherein in a single temperature step the binary semiconductor substrate is etched, a p-n junction with specific device characteristics is produced in the binary semiconductor substrate by diffusion of a dopant from the melt and a region of the ternary semiconductor of precise conductivity type and thickness is grown by virtue of a change in the melt characteristics when the etched binary semiconductor enters the melt.
Flowgraph models describing relationships between thermal and electrical parameters of devices and associated circuits
Light activated low level switch consisting of electroluminescent GaAs p-n diode and double emitter silicon transistor
Magnetic field quenching of enhanced pulses produced in silicon nuclear particle detectors upon irradiation by light particles and low energy gamma rays
Fabrication processes and techniques for improving n on p silicon solar cells
Effect of dimensions on quantum and photovoltaic energy conversion efficiency of germanium p-n semiconducting cells
Piezojunction effect in miniature solid state pressure transducer
CdS solar cell model noting spectral response, V-I characteristic and temperature variation
Li containing p-on-n and n-on-p Si cell degradation by bombardment noting carrier removal damage, annealing and radiation damage resistance
Nuclear radiation effects on junction capacitance of silicon p-n diode
A chopped electron beam induced current (EBIC) technique for the chacterization of back-surface field (BSF) solar cells is presented. It is shown that the effective recombination velocity of the low-high junction forming the back-surface field of BSF cells, in addition to the diffusion length and the surface recombination velocity of the surface perpendicular to both the p-n and low-high junctions, can be determined from the data provided by a single EBIC scan. The method for doing so is described and illustrated. Certain experimental considerations taken to enhance the quality of the EBIC data are also discussed.
The results are presented of a study to determine the effect of in-situ proton irradiation upon low temperature, low intensity performance of several cell types. The cell types were selected in an attempt to distinguish variations in temperature-dependent radiation resistance which could be attributed to the n-p or p-n structure, diffused or implanted junctions, crucible grown or float-zone type base material, and high or low base resistivity. The results indicate that while expected variations of performance occur at room temperature, all cell types degrade more or less similarly at lower temperatures with normalized degradation becoming increasingly rapid as temperature is reduced. Recommendations for an optimized cell for Jupiter probe use are included along with a definition of the testing required on these cells to insure good performance characteristics.