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At least 163 records · Page 9

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DOE OSTI2021

AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units interconnected through a network-on-chip (NoC), provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). Un-fortunately, designing a CGRA for a specific application domain involves enormous software/hardware engineering effort (e.g., designing the CGRA, map operations onto the CGRA, etc) and requires the exploration on a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc). Int his paper, we propose AURORA – a software/hardware co-design framework to automatically synthesize optimal CGRA given a set of applications of interest

Tan, Cheng↗

DOE OSTI2021

Companion Assisted Software Based Remote Attestation in SCADA Networks

Critical infrastructure such as power generation and water distribution systems have become a priority target in cyber warfare because of their recent computerization and introduction to the internet. As a result, Supervisory Control and Data Acquisition (SCADA) system security has become a hot topic in academic and industrial research. Among these topics, Remote Attestation is a security method intended to detect the presence of fileless malware in remote devices as they continue to operate. This allows for the detection of malware in the absence of long-term storage artifacts before symptoms of compromise begin to appear. In general, a trusted device (the verifier) makes a request for evidence of innocence from the untrusted device (the prover). In software-based schemes, the verifier can then measure the delay between its request and the prover’s response. If this delay is greater than the known computational time of the evidence gathering algorithm performed by the prover, then evidence may have been forged. Multi-hop networks often introduce too much network jitter to allow accurate measurement of prover response time, which limits the effectiveness of software based Remote Attestation in a real-world setting. In this work, we introduce a companion device that the verifier can trust to perform a subset of attestation, thereby removing any network jitter. This device is a Field Programmable Gate Array (FPGA) that is physically connected to the prover. We provide a communication protocol between the verifier, prover, and companion. To evaluate our scheme, we simulate it in a common SCADA network environment under normal and heavy traffic loads. Our simulations are performed in the discrete event network simulator NS-3, and we perform statistical analysis over our results to show that our scheme allows for tight timing constraints to be placed on the prover such that the verifier can more easily determine the validity of the evidence that it receives.

Johnson, William A.↗

DOE OSTI2021

Illuminating Galaxy Evolution at Cosmic Noon with ISCEA: the Infrared Satellite for Cosmic Evolution Astrophysics

ISCEA (Infrared Satellite for Cosmic Evolution Astrophysics) is a small astrophysics mission whose Science Goal is to discover how galaxies evolved in the cosmic web of dark matter at cosmic noon. Its Science Objective is to determine the history of star formation and its quenching in galaxies as a function of local density and stellar mass when the Universe was 3-5 Gyrs old (1.2 10 Mpc in each of 50 protocluster (cluster and cosmic web) fields at 1.2 < z < 2.1. ISCEA measures the star formation quenching factor in those fields, and galaxy kinematics with a precision < 50 km/s to deduce the 3D spatial distribution in each field. ISCEA will transform our understanding of galaxy evolution at cosmic noon. ISCEA is a small satellite observatory with a 30cm equivalent diameter aperture telescope with a FoV of 0.32 deg^2, and a multi-object spectrograph with a digital micro-mirror device (DMD) as its programmable slit mask. ISCEA will obtain spectra of 1000 galaxies simultaneously at an effective resolving power of R=1000, with 2.8"x2.8" slits, over the NIR wavelength range of 1.1 to 2.0 microns, a regime not accessible from the ground without large gaps in coverage. ISCEA will achieve a pointing accuracy of <= 2" FWHM over 200s. ISCEA will be launched into a Low Earth Orbit, with a prime mission of 2.5 years. ISCEA's space-qualification of DMDs opens a new window for spectroscopy from space, enabling revolutionary advances in astrophysics.

79 ASTRONOMY AND ASTROPHYSICS↗

DOE OSTI2022

Beam steering at the nanosecond time scale with an atomically thin reflector

Techniques to mold the flow of light on subwavelength scales enable fundamentally new optical systems and device applications. The realization of programmable, active optical systems with fast, tunable components is among the outstanding challenges in the field. Here, we experimentally demonstrate a few-pixel beam steering device based on electrostatic gate control of excitons in an atomically thin semiconductor with strong light-matter interactions. By combining the high reflectivity of a MoSe 2 monolayer with a graphene split-gate geometry, we shape the wavefront phase profile to achieve continuously tunable beam deflection with a range of 10°, two-dimensional beam steering, and switching times down to 1.6 nanoseconds. Our approach opens the door for a new class of atomically thin optical systems, such as rapidly switchable beam arrays and quantum metasurfaces operating at their fundamental thickness limit.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

NASA NTRS2010

Reconfigurable Fault Tolerance for FPGAs

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

Shuler, Robert, Jr.↗

NASA NTRS1985

Bubble memory module for spacecraft application

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Hayes, P. J.↗

NASA NTRS2018

C++ Resource Intelligent Compilation for GPU Enabled Applications

We are nearing the limits of Moore's Law with current computing technology. As industries push for more performance from smaller systems, alternate methods of computation such as Graphics Processing Units (GPUs) should be considered. Many of these systems utilize the Compute Unified Device Architecture (CUDA) to give programmers access to individual compute elements of the GPU for general purpose computing tasks. Direct access to the GPU's parallel multi-core architecture enables highly efficient computation and can drastically reduce the time required for complex algorithms or data analysis. Of course not all systems have a CUDA-enabled device to leverage, and so applications must consider optional support for users with these devices. Resource Intelligent Compilation (RIC) addresses this situation by enabling GPU-based acceleration of existing applications without affecting users without GPUs. Resource Intelligent Compilation (RIC) creates C/C++ modules that can be compiled to create a standard CPU version or GPU accelerated version of a program, depending on hardware availability. This is accomplished through a toolbox of programming strategies based on features of the CUDA API. Using this toolbox, existing applications can be modified with ease to support GPU acceleration, and new applications can be generated with just a few simple modifications. All of this culminates in an accelerated application for users with the appropriate hardware, with no performance impact to standard systems. This memorandum presents all the important features involved in supporting and implementing RIC and an example of using RIC to accelerate an existing mathematical model, without removing support for standard users. Through this memorandum, NASA engineers can acquire a set of guidelines to follow for RIC-compliant development, seamlessly accelerating C/C++ applications.

GPU↗

NASA NTRS1990

Quantized-"Gray-Scale" Electronic Synapses

Proposed array of programmable synaptic connections for electronic neural network applications offers multiple quantized levels of connection strength using only simple, two-terminal, binary microswitch devices. Subgrids in fine grid of programmable resistive connections connected externally in parallel to form coarser synaptic grid. By selection of pattern of connections in each subgrid, connection strength of synaptic node represented by that subgrid set at quantized "gray level". Device structures promise implementations of quantized-"gray-scale" synaptic arrays with very high density.

Lamb, James L.↗

DOE OSTI2024

Incompatibility as a Resource for Programmable Quantum Instruments

Quantum instruments represent the most general type of quantum measurement, as they incorporate processes with both classical and quantum outputs. In many scenarios, it may be desirable to have some “on-demand” device that is capable of implementing one of many possible instruments whenever the experimenter desires. We refer to such objects as programmable instrument devices (PIDs), and this paper studies PIDs from a resource-theoretic perspective. A physically important class of PIDs are those that do not require quantum memories to implement, and these are naturally “free” in this resource theory. Additionally, these free objects correspond precisely to the class of unsteerable channel assemblages in the study of channel steering. The traditional notion of measurement incompatibility emerges as a resource in this theory since any PID controlling an incompatible family of instruments requires a quantum memory to build. We identify an incompatibility preorder between PIDs based on whether one can be transformed into another using processes that do not require additional quantum memories. Necessary and sufficient conditions are derived for when such transformations are possible based on how well certain guessing games can be played using a given PID. Ultimately our results provide an operational characterization of incompatibility, and they offer semi-device-independent tests for incompatibility in the most general types of quantum instruments. Published by the American Physical Society 2024

Physics↗

NASA NTRS2019

Microsemi RTG4 Rev C Field Programmable Gate Array Single Event Effects (SEE) Heavy-Ion Test Report

The goal of this study was to perform an independent investigation of single event destructive and transient susceptibility of the Microsemi RTG4 device. The devices under test were the Microsemi RTG4 field programmable gate array (FPGA) Rev C. The devices under test will be referenced as the DUT or RTG4 Rev C throughout this document. The DUT was configured to have various test structures that are geared to measure specific potential susceptibilities of the device. DesignDevice susceptibility was determined by monitoring the DUT for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) was checked throughout heavy-ion testing by monitoring device current.

Field Programmable Gate Array (FPGA)↗

NASA NTRS2012

Flexible Architecture for FPGAs in Embedded Systems

Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface. Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state. Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application. This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

Clark, Duane I.↗

NASA NTRS1979

Aerospace Ground Equipment for model 4080 sequence programmer. A standard computer terminal is adapted to provide convenient operator to device interface

The Aerospace Ground Equipment (AGE) provides an interface between a human operator and a complete spaceborne sequence timing device with a memory storage program. The AGE provides a means for composing, editing, syntax checking, and storing timing device programs. The AGE is implemented with a standard Hewlett-Packard 2649A terminal system and a minimum of special hardware. The terminal's dual tape interface is used to store timing device programs and to read in special AGE operating system software. To compose a new program for the timing device the keyboard is used to fill in a form displayed on the screen.

Nissley, L. E.↗

DOE OSTI2019

Front-end electronic readout system for the Belle II imaging Time-Of-Propagation detector

The Time-Of-Propagation detector is a Cherenkov particle identification detector based on quartz radiator bars for the Belle II experiment at the SuperKEKB ee collider. The purpose of the detector is to identify the type of charged hadrons produced in ee collisions, and requires a single photon timing resolution below 100 picoseconds. A novel front-end electronic system was designed, built, and integrated to acquire data from the 8192 microchannel plate photomultiplier tube channels in the detector. Waveform sampling of these analog signals is done by switched-capacitor array application-specific integrated circuits. The processes of triggering, digitization of windows of interest, readout, and data transfer to the Belle II data acquisition system are managed by Xilinx Zynq-7000 programmable system on a chip devices.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2024

Elasticity-controlled jamming criticality in soft composite solids

Soft composite solids are made of inclusions dispersed within soft matrices. They are ubiquitous in nature and form the basis of many biological tissues. In the field of materials science, synthetic soft composites are promising candidates for building various engineering devices due to their highly programmable features. However, when the volume fraction of the inclusions increases, predicting the mechanical properties of these materials poses a significant challenge for the classical theories of composite mechanics. The difficulty arises from the inherently disordered, multi-scale interactions between the inclusions and the matrix. To address this challenge, we systematically investigated the mechanics of densely filled soft elastomers containing stiff microspheres. We experimentally demonstrate how the strain-stiffening response of the soft composites is governed by the critical scalings in the vicinity of a shear-jamming transition of the included particles. The proposed criticality framework quantitatively connects the overall mechanics of a soft composite with the elasticity of the matrix and the particles, and captures the diverse mechanical responses observed across a wide range of material parameters. The findings uncover a novel design paradigm of composite mechanics that relies on engineering the jamming properties of the embedded inclusions.

36 MATERIALS SCIENCE↗

DOE OSTI2022

Writable spin wave nanochannels in an artificial-spin-ice-mediated ferromagnetic thin film

We report magnonics, which employs spin-waves to transmit and process information, is a promising venue for low-power data processing. One of the major challenges is the local control of the spin-wave propagation path. Here, we introduce the concept of writable magnonics by taking advantage of the highly flexible reconfigurability and rewritability of artificial spin ice systems. Using micromagnetic simulations, we show that globally switchable spin-wave propagation and locally writable spin-wave nanochannels can be realized in a ferromagnetic thin film underlying an artificial pinwheel spin ice. The rewritable magnonics enabled by reconfigurable spin wave nanochannels provides a unique setting to design programmable magnonic circuits and logic devices for ultra-low power applications.

42 ENGINEERING↗

NASA NTRS1977

Robots and manipulator systems; Proceedings of the Second Conference on Remotely Manned Systems, Los Angeles, Calif., June 9-11, 1975

Attention is given to supervisory control of remote manipulation, an automatic device for measuring viscoelasticity, adaptable programmable assembly systems for teleoperator applications, and proximity sensor technology for manipulator end effectors. Also considered are control and stability problems of remote orbital capture, orbital servicing and remotely manned systems, gray-level transformations for interactive image enhancement, and the design of a three-fingered hand

Heer, E.↗

NASA NTRS1989

A programmable CCD driver circuit for multiphase CCD operation

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Ewin, Audrey J.↗

NASA NTRS1996

Clinical Verification of Image Warping as a Potential Aid for the Visually Handicapped

The bulk of this research was to designed determine potential of the Programmable Remapper (PR) as a device to enhance vision for the visually handicapped. This research indicated that remapping would have potential as a low vision device if the eye position could be monitored with feedback to specify the proper location of the remapped image. This must be accomplished at high rate so that there is no lag of the image behind the eye position. Since at this time, there is no portable eye monitor device (at a reasonable cost) that will operate under the required conditions, it would not be feasible to continue with remapping experiments for patients with central field defects. However, since patients with peripheral field defects do not have the same eye positioning requirements, they may indeed benefit from this technology. Further investigations must be performed to determine plausibility of this application of remapping.

Loshin, David↗