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At least 163 records · Page 9

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Vasile, Stefan↗

Combined Thermomechanical and Environmental Durability of Environmental Barrier Coating Systems on SiC/SiC Ceramic Matrix Composites

Environmental barrier coatings (EBCs) and SiC/SiC ceramic matrix composites (CMCs) will play a crucial role in next generation turbine engines for hot-section component applications. The development of prime-reliant environmental barrier coatings is essential to the EBC-CMC system durability, ensuring the successful implementations of the high temperature and lightweight engine component technologies for engine applications.This paper will emphasize recent NASA environmental barrier coating and CMC developments for SiC/SiC turbine airfoil components, utilizing advanced coating compositions and processing methods. The emphasis has been particularly placed on thermomechanical and environment durability evaluations of EBC-CMC systems. We have also addressed the integration of the EBCs with advanced SiC/SiC CMCs, and studied the effects of combustion environments and Calcium-Magnesium-Alumino-Silicate (CMAS) deposits on the durability of the EBC-CMC systems under thermal gradient and mechanical loading conditions. Advanced environmental barrier coating systems, including multicomponent rare earth silicate EBCs and HfO2-Si based bond coats, will be discussed for the performance improvements to achieve better temperature capability and CMAS resistance for future engine operating conditions.

Ceramic Matrix Composites↗

Thermodynamic data for fifty reference elements

This report is a compilation of thermodynamic functions of 50 elements in their standard reference state. The functions are C(sub p)(sup 0), (H(sup 0)(T) - H(sup 0)(0)), S(sup 0)(T), and -(G(sup 0)(T) - H(sup 0)(O)) for the elements Ag, Al, Ar, B, Ba, Be, Br2, C, Ca, Cd, Cl2, Co, Cr, Cs, Cu, F2, Fe, Ge, H2, He, Hg, I2, K, Kr, Li, Mg, Mn, Mo, N2, Na, Nb, Ne, Ni, O2, P, Pb, Rb, S, Si, Sn, Sr, Ta, Th, Ti, U, V, W, Xe, Zn, and Zr. Deuterium D2 and electron gas e(sup -) are also included. The data are tabulated as functions of temperature as well as given in the form of least-squares coefficients for two functional forms for C(sub p)(sup 0) with integration constants for enthalpy and entropy. One functional form for C(sub p)(sup 0) is a fourth-order polynomial and the other has two additional terms, one with T(exp -1) and the other with T(exp -2). The gases Ar, D2, e(sup -), H2, He, Kr, N2, Ne, O2, and Xe are tabulated for temperatures from 100 to 20,000 K. The remaining gases Cl2 and F2 are tabulated from 100 to 6000 K and 1000 to 6000 K. The second functional form for C(sub p)(sup 0) has an additional interval from 6000 to 20,000 K for the gases tabulated to 20,000 K. The fits are constrained so that the match at the common temperature endpoints. The temperature ranges for the condensed species vary with range of the data, phase changes, and shapes of the C(sub p)(sup 0) curves.

Mcbride, Bonnie J.↗

Thermodynamic Data for Fifty Reference Elements

This report is a compilation of thermodynamic functions of 50 elements in their reference state. The functions are: C(sup 0, sub p), {H(T)-H(sup 0)(0)}, S(sup 0)(T), and - {G(sup 0)(T) - H(sup 0)(0)} for the elements Ag, Al, Ar, B, Ba, Be, Br2, C, Ca, Cd, Cl2, Co, Cr, Cs, Cu, F2, Fe, Ge, H2, He, Hg, I2, K, Kr, Li, Mg, Mn, Mo, N2, Na, Nb, Ne, Ni, O2, P, Pb, Rb, S, Si, Sn, Sr, Th, Th, Ti, U, V, W, Xe, Zn, and Zr. Deuterium D, and electron gas e(sup -) are also included. The data are tabulated as functions of temperature as well as given in the form of least-squares coefficients for two functional forms for C(sup 0, sub p) with integration constants for enthalpy and entropy. One functional form for C(sup 0, sub p) is a fourth-order polynomial and the other has two additional terms, one with T(sup -1) and the other with T(sup -2). The gases Ar, D2, e(sup -), H2, He, Kr, N2, Ne, O2, and Xe are tabulated for temperatures from 100 to 20 000 K. The remaining gases Cl2 and F2 are tabulated from 100 to 6000 K. The polynomial functional form for C(sup 0, sub p) for all these gases is split into two temperature intervals of 200 to 1000 K and 1000 to 6000 K. The second functional form for (sup 0, sub p) has an additional interval from 6000 to 20 000 K for the gases tabulated to 20 000 K. The fits are constrained so that the properties match at the common temperature endpoints. The temperature ranges for the condensed species vary with range of the data, phase changes, and shapes of the C(sup 0, sub p) curves.

McBride, Bonnie J.↗

Progress Towards Prolonged Deployment of SiC JFET-R ICs Into Previously Inaccessible Hostile Environments

This invited presentation describes demonstration of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. SiC junction field effect transistor-resistor (JFET-R) ICs with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [2], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [3]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C T-span) without significant change in signal (input /output) or power supply voltages [4]. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards this end, the processing that forms the SiC JFETs and resistors (without interconnect) for the NASA Glenn “Generation 12” design prototype JFET-R ICs was conducted at GE Research. Once the COVID-delayed IC interconnect and bond pad fabrication processing on these wafers is completed at NASA Glenn, the resulting chips will be packaged and oven-tested [5]. It is expected that further technology transfer to complete commercial production will lower investment and risk barriers to useful application deployment. For NASA, an initial high-value deployment is opening the Venus surface to extended missions for robotic scientific exploration.

Silicon Carbide↗

Displacement Damage in Bipolar Linear Integrated Circuits

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Rax, B. G.↗

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗

Lattice-matched heteroepitaxy of wide gap ternary compound semiconductors

A variety of applications are identified for heteroepitaxial structures of wide gap I-III-VI(sub 2) and II-IV-V(sub 2) semiconductors, and are assessed in comparison with ternary III-V alloys and other wide gap materials. Non-linear optical applications of the I-III-VI(sub 2) and II-IV-V(sub 2) compound heterostructures are discussed, which require the growth of thick epitaxial layers imposing stringent requirements on the conditions of heteroepitaxy. In particular, recent results concerning the MOCVD growth of ZnSi(x)Ge(1-x)P2 alloys lattice matching Si or GaP substrates are reviewed. Also, heterostructures of Cu(z)Ag(1-z)GaS2 alloys that lattice-match Si, Ge, GaP, or GaAs substrates are considered in the context of optoelectronic devices operating in the blue wavelength regime. Since under the conditions of MOCVD, metastable alloys of the II-IV-V(sub 2) compounds and group IV elements are realized, II-IV-V(sub 2) alloys may also serve as interlayers in the integration of silicon and germanium with exactly lattice-matched tetrahedrally coordinated compound semiconductors, e.g. ZnSi(x)Ge(1-x)P2.

Bachmann, Klaus J.↗

Line strengths, collision strengths and excitation rates for multiply-charged silicon ions

In the present paper, the line strengths, collision strengths, and rate coefficients are calculated for a variety of transitions in multiply charged silicon ions from Si(VI) to Si(XIV). The line strengths are obtained by using Clementi wave functions for the ground-state configuration, and excited-state wave functions generated by a semiempirical method. The collision strengths are calculated in an LS coupling scheme in the distorted-wave approximation, neglecting exchange except for the helium-like transitions. These results are then integrated over a Maxwellian velocity distribution function to yield rate coefficients. The rates are presented graphically and also in terms of a two-parameter fit.

Davis, J.↗

Mu-Spec - A High Performance Ultra-Compact Photon Counting spectrometer for Space Submillimeter Astronomy

We have designed and are testing elements of a fully integrated submillimeter spectrometer based on superconducting microstrip technology. The instrument can offer resolving power R approximately 1500, and its high frequency cutoff is set by the gap of available high performance superconductors. All functions of the spectrometer are integrated - light is coupled to the microstrip circuit with a planar antenna, the spectra discrimination is achieved using a synthetic grating, orders are separated using planar filter, and detected using photon counting MKID detector. This spectrometer promises to revolutionize submillimeter spectroscopy from space. It replaces instruments with the scale of 1m with a spectrometer on a 10 cm Si wafer. The reduction in mass and volume promises a much higher performance system within available resource in a space mission. We will describe the system and the performance of the components that have been fabricated and tested.

Moseley, H.↗

Total integrated dose testing of solid-state scientific CD4011, CD4013, and CD4060 devices by irradiation with CO-60 gamma rays

The total integrated dose response of three CMOS devices manufactured by Solid State Scientific has been measured using CO-60 gamma rays. Key parameter measurements were made and compared for each device type. The data show that the CD4011, CD4013, and CD4060 produced by this manufacturers should not be used in any environments where radiation levels might exceed 1,000 rad(Si).

Dantas, A. R. V.↗

Flat-plate solar array progress and plans

The Flat-Plate Solar Array Project (FSA), sponsored by the U.S. Department of Energy (DOE) and managed by the Jet Propulsion Laboratory (JPL), has achieved progress in a broad range of technical activities since that reported at the Fourth European Communities Conference. A particularly important analysis has been completed recently which confirms the adoption into practice by the U.S. Photovoltaic (PV Industry, of all the low-cost module technology elements proposed at the 16th Project Integration Meeting for a $2.80/Wp (1980 U.S. Dollars) design approach in the fall of 1980. This work presents along with a projection, using the same techniques, for what is believed to be a very credible ribbon-based module design for less that $0.55/Wp (1980 U.S. Dollars). Other areas to be reported upon include low-cost Si feedstock refinement; ribbon growth; process sequence development for cells; environmental isolation; engineering science investigations; and module testing progress.

Callaghan, W. T.↗

Feature Profile Evolution of SiO2 Trenches In Fluorocarbon Plasmas

Etching of silicon microstructures for semiconductor manufacturing in chlorine plasmas has been well characterized. The etching proceeds in a two-part process, where the chlorine neutrals passivate the Si surface and then the ions etch away SiClx. However, etching in more complicated gas mixtures and materials, such as etching of SiO2 in Ar/C4F8, requires knowledge of the ion and neutral distribution functions as a function of angle and velocity, in addition to modeling the gas surface reactions. In order to address these needs, we have developed and integrated a suite of models to simulate the etching process from the plasma reactor level to the feature profile evolution level. This arrangement allows for a better understanding, control, and prediction of the influence of equipment level process parameters on feature profile evolution. We are currently using the HPEM (Hybrid Plasma Equipment Model) and PCMCM (Plasma Chemistry Monte Carlo Model) to generate plasma properties and ion and neutral distribution functions for argon/fluorocarbon discharges in a GEC Reference Cell. These quantities are then input to the feature scale model, Simulation of Profile Evolution by Level Sets (SPELS). A surface chemistry model is used to determine the interaction of the incoming species with the substrate material and simulate the evolution of the trench profile. The impact of change of gas pressure and inductive power on the relative flux of CFx and F to the wafer, the etch and polymerization rates, and feature profiles will be examined. Comparisons to experimental profiles will also be presented.

Hwang, Helen↗

Doping Scheme in Atomic Chain Electronics

Due to the dramatic reduction in MOS size, there appear many unwanted effects. In these small devices, the number of dopant atoms in the channel is not macroscopic and electrons may suffer significantly different scattering from device to device since the spatial distribution of dopant atoms is no longer regarded as continuous. This prohibits integration, while it is impossible to control such dopant positions within atomic scale. A fundamental solution is to create electronics with simple but atomically precise structures, which could be fabricated with recent atom manipulation technology. All the constituent atoms are placed as planned, and then the device characteristics are deviation-free, which is mandatory for integration. Atomic chain electronics belongs to this category. Foreign atom chains or arrays form devices, and they are placed on the atomically flat substrate surface. We can design the band structure and the resultant Fermi energy of these structures by manipulating the lattice constant. Using the tight-binding theory with universal parameters, it has been predicted that isolated Si chains and arrays are metallic, Mg chains are insulating, and Mg arrays have metallic and insulating phases [1]. The transport properties along a metallic chain have been studied, emphasizing the role of the contact to electrodes [2]. For electronic applications, it is essential to establish a method to dope a semiconducting chain, which is to control the Fermi energy position without altering the original band structure. If we replace some of the chain atoms with dopant atoms randomly, the electrons will see random potential along die chain and will be localized strongly in space (Anderson localization). However, if we replace periodically, although the electrons can spread over the chain, there will generally appear new bands and band gaps reflecting the new periodicity of dopant atoms. This will change the original band structure significantly. In order to overcome this dilemma, we may place a dopant atom beside the chain at every N lattice periods (N > 1). Because of the periodic arrangement of pant atoms, we can avoid the unwanted Anderson localization. Moreover, since the dopant atoms do not constitute the chain, the overlap interaction between them is minimized, and the band structure modification can be made smallest. Some tight-binding results will be discussed to demonstrate the present idea.

Toshishige, Yamada↗

Growing Aligned Carbon Nanotubes for Interconnections in ICs

A process for growing multiwalled carbon nanotubes anchored at specified locations and aligned along specified directions has been invented. Typically, one would grow a number of the nanotubes oriented perpendicularly to a silicon integrated-circuit (IC) substrate, starting from (and anchored on) patterned catalytic spots on the substrate. Such arrays of perpendicular carbon nanotubes could be used as electrical interconnections between levels of multilevel ICs. The process (see Figure 1) begins with the formation of a layer, a few hundred nanometers thick, of a compatible electrically insulating material (e.g., SiO(x) or Si(y)N(z) on the silicon substrate. A patterned film of a suitable electrical conductor (Al, Mo, Cr, Ti, Ta, Pt, Ir, or doped Si), having a thickness between 1 nm and 2 m, is deposited on the insulating layer to form the IC conductor pattern. Next, a catalytic material (usually, Ni, Fe, or Co) is deposited to a thickness between 1 and 30 nm on the spots from which it is desired to grow carbon nanotubes. The carbon nanotubes are grown by plasma-enhanced chemical vapor deposition (PECVD). Unlike the matted and tangled carbon nanotubes grown by thermal CVD, the carbon nanotubes grown by PECVD are perpendicular and freestanding because an electric field perpendicular to the substrate is used in PECVD. Next, the free space between the carbon nanotubes is filled with SiO2 by means of CVD from tetraethylorthosilicate (TEOS), thereby forming an array of carbon nanotubes embedded in SiO2. Chemical mechanical polishing (CMP) is then performed to remove excess SiO2 and form a flat-top surface in which the outer ends of the carbon nanotubes are exposed. Optionally, depending on the application, metal lines to connect selected ends of carbon nanotubes may be deposited on the top surface. The top part of Figure 2 is a scanning electron micrograph (SEM) of carbon nanotubes grown, as described above, on catalytic spots of about 100 nm diameter patterned by electron-beam lithography. These and other nanotubes were found to have lengths ranging from 2 to 10 m and diameters ranging from 30 to 200 nm, the exact values of length depending on growth times and conditions and the exact values of diameter depending on the diameters and thicknesses of the catalyst spots. The bottom part of Figure 2 is an SEM of an embedded array of carbon nanotubes after CMP.

Li, Jun↗

Process for Smoothing an Si Substrate after Etching of SiO2

A reactive-ion etching (RIE) process for smoothing a silicon substrate has been devised. The process is especially useful for smoothing those silicon areas that have been exposed by etching a pattern of holes in a layer of silicon dioxide that covers the substrate. Applications in which one could utilize smooth silicon surfaces like those produced by this process include fabrication of optical waveguides, epitaxial deposition of silicon on selected areas of silicon substrates, and preparation of silicon substrates for deposition of adherent metal layers. During etching away of a layer of SiO2 that covers an Si substrate, a polymer becomes deposited on the substrate, and the substrate surface becomes rough (roughness height approximately equal to 50 nm) as a result of over-etching or of deposition of the polymer. While it is possible to smooth a silicon substrate by wet chemical etching, the undesired consequences of wet chemical etching can include compromising the integrity of the SiO2 sidewalls and undercutting of the adjacent areas of the silicon dioxide that are meant to be left intact. The present RIE process results in anisotropic etching that removes the polymer and reduces height of roughness of the silicon substrate to less than 10 nm while leaving the SiO2 sidewalls intact and vertical. Control over substrate versus sidewall etching (in particular, preferential etching of the substrate) is achieved through selection of process parameters, including gas flow, power, and pressure. Such control is not uniformly and repeatably achievable in wet chemical etching. The recipe for the present RIE process is the following: Etch 1 - A mixture of CF4 and O2 gases flowing at rates of 25 to 75 and 75 to 125 standard cubic centimeters per minute (stdcm3/min), respectively; power between 44 and 55 W; and pressure between 45 and 55 mtorr (between 6.0 and 7.3 Pa). The etch rate lies between approximately equal to 3 and approximately equal to 6 nm/minute. Etch 2 - O2 gas flowing at 75 to 125 stdcm3/min, power between 44 and 55 W, and pressure between 50 and 100 mtorr (between 6.7 and 13.3 Pa).

Turner, Tasha↗

SEM analysis of ionizing radiation effects in linear integrated circuits

A successful diagnostic technique was developed using a scanning electron microscope (SEM) as a precision tool to determine ionization effects in integrated circuits. Previous SEM methods radiated the entire semiconductor chip or major areas. The large area exposure methods do not reveal the exact components which are sensitive to radiation. To locate these sensitive components a new method was developed, which consisted in successively irradiating selected components on the device chip with equal doses of electrons /10 to the 6th rad (Si)/, while the whole device was subjected to representative bias conditions. A suitable device parameter was measured in situ after each successive irradiation with the beam off.

Stanley, A. G.↗

Quantitative simultaneous multi-element microprobe analysis using combined wavelength and energy dispersive systems

A combined WDS-EDS system obviates the severe X-ray peak overlap problems encountered with Na, Mg, Al and Si common to pure EDS systems. By application of easily measured empirical correction factors for pulse pile-up and peak overlaps which are normally observed in the analysis of silicate minerals, the accuracy of analysis is comparable with that expected for WDS electron microprobe analyses. The continuum backgrounds are subtracted for the spectra by a spline fitting technique based on integrated intensities between the peaks. The preprocessed data are then reduced to chemical analyses by existing data reduction programs.

Walter, L. S.↗