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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Can improved canopy light transmission ameliorate loss of photosynthetic efficiency in the shade? An investigation of natural variation in Sorghum bicolor

Abstract Previous studies have found that maximum quantum yield of CO2 assimilation (Φ CO2,max,app) declines in lower canopies of maize and miscanthus, a maladaptive response to self-shading. These observations were limited to single genotypes, leaving it unclear whether the maladaptive shade response is a general property of this C4 grass tribe, the Andropogoneae. We explored the generality of this maladaptation by testing the hypothesis that erect leaf forms (erectophiles), which allow more light into the lower canopy, suffer less of a decline in photosynthetic efficiency than drooping leaf (planophile) forms. On average, Φ CO2,max,app declined 27% in lower canopy leaves across 35 accessions, but the decline was over twice as great in planophiles than in erectophiles. The loss of photosynthetic efficiency involved a decoupling between electron transport and assimilation. This was not associated with increased bundle sheath leakage, based on 13C measurements. In both planophiles and erectophiles, shaded leaves had greater leaf absorptivity and lower activities of key C4 enzymes than sun leaves. The erectophile form is considered more productive because it allows a more effective distribution of light through the canopy to support photosynthesis. We show that in sorghum, it provides a second benefit, maintenance of higher Φ CO2,max,app to support efficient use of that light resource.

54 ENVIRONMENTAL SCIENCES↗
DOE OSTI2022

Ultra-Fast Resonant DC Breaker

This project’s focus was to create an ultra-fast resonant hybrid dc circuit breaker for medium voltage electric systems. Medium voltage DC systems offer higher efficiency, additional resiliency, more controllability, and greater flexibility over comparable AC systems. Although technically, medium voltage DC systems are more attractive than their AC counterparts, no solution exists for the protection of medium voltage DC systems, and thus one cannot build a reliable MVDC system. This research will fill the technology gap, providing a MVDC protection solution, allowing mass adoption and proliferation of MVDC systems. MVDC systems will allow greater integration of renewable energy sources, higher efficiency of transmission and distribution, reduced losses in transmission lines, reduce carbon emissions, and higher electric power reliability.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1965

Results of tests at Goonhilly using the experimental communication satellites Telstar I and Telstar II

The first active communication satellite-Telstar I-was launched from Cape Canaveral by the National Aeronautics and Space Administration (NASA) on 10th July, 1962, and was later followed by Relay and Telstar II. Since the 10th July, 1962, many tests and demonstrations of television, multichannel telephony and telegraphy, facsimile and data transmission have been made via these experimental satellites. In addition, much data has been accumulated on microwave propagation, earth-station receiving system noise temperatures and satellite tracking accuracy. Such tests and data will be of considerable value for the planning and design of future operational communication-satellite systems.

GROUND STATION↗
NASA NTRS1972

A versatile Mossbauer spectrometer and its applications in vibration measurement

A Fe-57 Mossbauer spectrometer, equally efficient in transmission and reflection geometries, is described. The radiation detector consists of a 1.524- by 5.08 by 5.08-cm rectangular NaI(Tl) crystal with a hole 1.524 cm in diameter. The front and back faces of the crystal are covered with beryllium windows 0.0127 cm thick and 3.81 cm in diameter. The energy of the radiation accepted for counting ranges from 6.3 keV conversion X-rays to the 14.4 keV reemitted gamma rays. The spectrometer was used to measure various types of low frequency (10 Hz) and low amplitude (0.254 mm) periodic motion of steel specimens.

Singh, J. J.↗
NASA NTRS1976

Microwave transmission system for space power

The system considered makes use of a combined dipole antenna and rectifier. The dipole elements feed a balanced transmission line low-pass filter. A description of a laboratory model microwave power transmission system is given and a higher-power project with a longer range is discussed. Space power transmission experiments are also considered. It is pointed out that the investigations have shown that high overall transmission link efficiencies are possible.

Dickinson, R. M.↗
NASA NTRS1980

Comparison of Low Earth Orbit and Geosynchronous Earth Orbits

The technological, environmental, social, and political ramifications of low Earth orbits as compared to geosynchronous Earth orbits for the solar power satellite (SPS) are assessed. The capital cost of the transmitting facilities is dependent on the areas of the antenna and rectenna relative to the requirement of high efficiency power transmission. The salient features of a low orbit Earth orbits are discussed in terms of cost reduction efforts.

Drummond, J. E.↗
NASA NTRS1991

A parallel-pipelined architecture for a multi carrier demodulator

Analog devices have been used for processing the information on board the satellites. Presently, digital devices are being used because they are economical and flexible as compared to their analog counterparts. Several schemes of digital transmission can be used depending on the data rate requirement of the user. An economical scheme of transmission for small earth stations uses single channel per carrier/frequency division multiple access (SCPC/FDMA) on the uplink and time division multiplexing (TDM) on the downlink. This is a typical communication service offered to low data rate users in commercial mass market. These channels usually pertain to either voice or data transmission. An efficient digital demodulator architecture is provided for a large number of law data rate users. A demodulator primarily consists of carrier, clock, and data recovery modules. This design uses principles of parallel processing, pipelining, and time sharing schemes to process large numbers of voice or data channels. It maintains the optimum throughput which is derived from the designed architecture and from the use of high speed components. The design is optimized for reduced power and area requirements. This is essential for satellite applications. The design is also flexible in processing a group of a varying number of channels. The algorithms that are used are verified by the use of a computer aided software engineering (CASE) tool called the Block Oriented System Simulator. The data flow, control circuitry, and interface of the hardware design is simulated in C language. Also, a multiprocessor approach is provided to map, model, and simulate the demodulation algorithms mainly from a speed view point. A hypercude based architecture implementation is provided for such a scheme of operation. The hypercube structure and the demodulation models on hypercubes are simulated in Ada.

Kwatra, S. C.↗
NASA NTRS1992

Large transient fault current test of an electrical roll ring

The space station uses precision rotary gimbals to provide for sun tracking of its photoelectric arrays. Electrical power, command signals and data are transferred across the gimbals by roll rings. Roll rings have been shown to be capable of highly efficient electrical transmission and long life, through tests conducted at the NASA Lewis Research Center and Honeywell's Satellite and Space Systems Division in Phoenix, AZ. Large potential fault currents inherent to the power system's DC distribution architecture, have brought about the need to evaluate the effects of large transient fault currents on roll rings. A test recently conducted at Lewis subjected a roll ring to a simulated worst case space station electrical fault. The system model used to obtain the fault profile is described, along with details of the reduced order circuit that was used to simulate the fault. Test results comparing roll ring performance before and after the fault are also presented.

Yenni, Edward J.↗
NASA NTRS1991

Large transient fault current test of an electrical roll ring

The Space Station Freedom uses precision rotary gimbals to provide for sun tracking of its photoelectric arrays. Electrical power, command signals, and data are transferred across the gimbals by roll rings. Roll rings have been shown to be capable of highly efficient electrical transmission and long life, through tests conducted at the NASA Lewis Research Center and Honeywell's Satellite and Space Systems Division in Phoenix, AZ. Large potential fault currents inherent to the power system's DC distribution architecture have brought about the need to evaluate the effects of large transient fault currents on roll rings. A test recently conducted at Lewis subjected a roll ring to a simulated worst case space station electrical fault. The system model used to obtain the fault profile is described, along with details of the reduced order circuit that was used to simulate the fault. Test results comparing roll ring performance before and after the fault are also presented.

Yenni, Edward J.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

Architecture and implementation considerations of a high-speed Viterbi decoder for a Reed-Muller subcode

The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.

Lin, Shu↗