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In one inventive concept, an ink includes a precursor of a graphene analogue, a thickener, and a solvent. In another inventive concept, an ink includes a graphene analogue, a thickener, and a solvent. In yet another inventive concept, an aerogel includes a three-dimensional printed structure having printed features comprised of two dimensional sheets of a graphene analogue.
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Log-Structured Merge Tree (LSM-tree) based key-value stores excel in write-intensive environments but suffer from data duplication, consuming up to 49% of storage space in LSM-tree-based key-value store deployments. Traditional solutions like compression and coarse-grained file system-level deduplication introduce overhead or have limited effectiveness. In this study, we propose DedupKV, a fine-grained deduplication framework tailored for LSM-tree, maximizing data reduction efficiency while minimizing write stalls and read overheads. DedupKV features three key innovations: (1) FLUSH-integrated inline deduplication, which removes duplicates during memory-to-storage writes; (2) WAL file-based offline deduplication, repurposing write-ahead logs to avoid double writes; and (3) elastic execution, dynamically balancing inline and offline deduplication based on memory pressure and workload intensity. Additionally, dynamic granularity management reduces deduplication metadata overhead. We implemented these four ideas in RocksDB for the first time and conducted experiments in a Linux environment. Our evaluation shows that WAL file-based offline deduplication and DedupKV outperform BlobDB by 33% and 23%, respectively, in write-heavy workloads, while reducing write amplification by 1.2 ×, 2 ×, and 1.6 × for real KV datasets.
In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.
Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times. The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device. The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.
A compact, reliable controller for an electrically erasable, programmable read-only memory (EEPROM) has been developed specifically for a space-flight application. The design may be adaptable to other applications in which there are requirements for reliability in general and, in particular, for prevention of inadvertent writing of data in EEPROM cells. Inadvertent writes pose risks of loss of reliability in the original space-flight application and could pose such risks in other applications. Prior EEPROM controllers are large and complex and do not provide all reasonable protections (in many cases, few or no protections) against inadvertent writes. In contrast, the present controller provides several layers of protection against inadvertent writes. The controller also incorporates a write-time monitor, enabling determination of trends in the performance of an EEPROM through all phases of testing. The controller has been designed as an integral subsystem of a system that includes not only the controller and the controlled EEPROM aboard a spacecraft but also computers in a ground control station, relatively simple onboard support circuitry, and an onboard communication subsystem that utilizes the MIL-STD-1553B protocol. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD- 1553B is commonly used in defense and space applications.) The intent was to both maximize reliability while minimizing the size and complexity of onboard circuitry. In operation, control of the EEPROM is effected via the ground computers, the MIL-STD-1553B communication subsystem, and the onboard support circuitry, all of which, in combination, provide the multiple layers of protection against inadvertent writes. There is no controller software, unlike in many prior EEPROM controllers; software can be a major contributor to unreliability, particularly in fault situations such as the loss of power or brownouts. Protection is also provided by a powermonitoring circuit.
The theoretical construct under which technical writing exercises operate and results from a survey distributed to a random sample of teachers of technical writing are described. The survey, part of a study to develop materials that did not stress prescriptive formats, drew on diverse elements in report writing to enhance writing as a process. Areas of agreement and disagreement related to problem solving, paper evaluation, and individualizing instruction were surveyed. Areas of concern in contemplating the composition process include: (1) the need to create an environment that helps students want to succeed, (2) the role of peer group activity in helping some students who might not respond through lecture or individual study, and (3) encouraging growth in abilities and helping motivate students' interest in writing projects through relevant assignments or simulations students perceive as relevant.
Edge enhancement of an input image by four-wave mixing a first write beam with a second write beam in a photorefractive crystal, GaAs, was achieved for VanderLugt optical correlation with an edge enhanced reference image by optimizing the power ratio of a second write beam to the first write beam (70:1) and optimizing the power ratio of a read beam, which carries the reference image to the first write beam (100:701). Liquid crystal TV panels are employed as spatial light modulators to change the input and reference images in real time.
The flourishing development of neural networks that require exponentially growing amounts of data has presented an elevated demand for memory footprint. To address this, researchers have been exploring hardware accelerators with innovative memory architectures like 3D memory. These 3D memory architectures offer enhanced storage capacity and processing capabilities, at a cost of rising on-chip temperature during operation. Hafnium Zirconium Oxide (HZO) based Ferroelectric Random Access Memory (FeRAM) is a promising nonvolatile memory candidate in neural network hardware accelerators for its outstanding write performance and reliability. However, its implementation in the architecture regarding the temperature-dependent ferroelectric switching behavior has not been well studied. In this work, we study the thermal impacts on polarization switching through experimental devices and simulation results. We conduct the circuit and architecture-level simulations to showcase that one can exploit this temperature rise to reduce FeRAM's write voltage and write energy due to its unique temperature-activated polarization switching mechanisms. As the on-chip temperature increases to 351K (ambient temperature at 300K) due to neural network workloads, the access energy per bit can be reduced by 27.6% when a dynamic write voltage is applied.
The importance of technical writing as a separate discipline is suggested. Some specific areas addressed were: technical writing skills industry needs, definitions of technical writing, the hows and whys of inhouse writing, and the nature of the composing process in technical comunication.
Teaching audience analysis, as practiced in a technical writing course for engineering students, is discussed. Audience analysis is described as the task of defining the audience for a particular piece of writing and determining those characteristics of the audience which constrain the writer and effect reception of the message. A mature technical writing style that shows the tension produced when a text is written to be read and understood is considered in terms of audience analysis. Techniques include: (1) conveying to students the concept that a reader with certain expectations exist, (2) team teaching to preserve the context of a given technical discipline, and (3) assigning a technical report that addresses a variety of readers, thus establishing the complexity of audience oriented writing.
Writing problems are addressed which are often encountered in technical documents and preferences are indicated (Langley's) when authorities do not agree. It is directed toward professional writers, editors, and proofreaders. Those whose profession lies in other areas (for example, research or management), but who have occasion to write or review others' writing will also find this information useful. A functional attitude toward grammar and punctuation is presented. Chapter 1 on grammar presents grammatical problems related to each part of speech. Chapter 2 on sentence structure concerns syntax, that is, effective arrangement of words, with emphasis on methods of revision to improve writing effectiveness. Chapter 3 addresses punctuation marks, presenting their function, situations when they are required or incorrect, and situations when they are appropriate but optional. Chapter 4 presents capitalization, which is mostly a matter of editorial style and preference rather than a matter of generally accepted rules. An index and glossary are included.
Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.
The same elements can form different compounds with widely different physical properties. Synthesis of a single-phase material is commonly achieved by controlling experimental conditions. Synthesizing materials that incorporate multiple specific spatially distributed chemical phases is often challenging, especially if different phases must be organized into well-defined spatial patterns. Here, we present an efficient solid reaction laser annealing (SRLA) approach to directly write regions of different local chemical compositions. We demonstrate the practical utility of our approach by locally writing microscale patterns of distinct chemical phases in vanadium oxide thin films. Specifically, we achieved the controlled local recrystallization of a uniform V 2 O 3 matrix into VO 2 , V 3 O 5 , and V 4 O 7 regions exhibiting sharp 1st- and 2nd-order metal–insulator phase transitions over a wide range of critical temperatures, i.e., a characteristic feature of select vanadium oxides that is extremely sensitive to even minute structural or compositional imperfections. We utilized the local chemical phase writing to pattern spiking oscillators with distinct electrical behavior directly in the thin film sample without employing elaborate lithography fabrication. Our laser tuning local chemical composition opens a pathway to synthesize a wide range of artificially micropatterned composite materials, with precision and control unattainable in conventional material synthesis methods.
In this article, we perform a comprehensive experimental and modeling study into the scaling of vertical 2T-nC ferroelectric random-access memory (FeRAM) hybrid cell to demonstrate a high performance and high-density 3D capacitor memory. We demonstrate: i) first time successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectricmetal (MFM) stack on top of Si CMOS transistors; ii) successful experimental operation of the memory cell, including the quasi-nondestructive read out (QNRO) of the polarization without write back after 106 read cycles; iii) the write bit line (WBL) heavily screens the coupling between neighboring strings, making it a minor concern; V ) aggressive stacking of the WBLs, i.e., number of MFMs in a string, could facilitate the self-boosting during write operation due to ferroelectric linear capacitance (CFE), which allows self-boosted inhibition for Vw/2 scheme and worsens the Vw/3 scheme as disturb increases to intolerable 2Vw/3; v) aggressive horizontal scaling significantly increases the read disturb to cells on neighboring planes due to capacitance between two WBLs (Cz).
Analyze 2D time- and energy-resolved data, such as from a pump-probe spectroscopy experiment. User can select and input different peak shapes/ functions and background types to first fit a ground state/ unperturbed spectrum. This would be similar to how standard spectroscopy data is fit. Subsequently, to describe the time domain, users can choose functions that describe the temporal dynamics of one or more spectral features, such as a peak amplitude, peak position, etc. These time dynamics functions can be added or convoluted (e.g. describing an instrument response function) with each other. Functionality to integrate implicit variables leading to distributions of certain parameters/ functions is in development. Alternatively, 2D data can be analyzed one time step at a time to get an idea of the time dynamics of the system before deploying the global 2D fit described above. Typically people write custom software for this purpose. During my PhD I've seen five internal LBL and external researchers write one-off code in different languages to analyze time- and energy-resolved spectra. While this was specifically was for a laser pump - X-ray probe spectroscopy experiment, I'm trying to write a general package for the time-resolved spectroscopy community.
The output of a molecular dynamics simulation is a data file containing properties of the motion of the simulated particles as a function of time (e.g., positions, velocities). From this output, scientists can extract various properties which give insight into the physics of the system; for example, the radial distribution function can be computed from the particle positions, which gives insight into how close the system is to melting or freezing. Many publicly available codes to perform molecular dynamics simulations exist and have been well adopted by the scientific community (e.g., LAMMPS, VASP). However, it remains standard practice for scientists to write their own post-processing scripts to extract various properties of interest from the molecular dynamics simulation data. Since in many cases scientists are interested in the same set of “textbook” properties, there is a large duplication of effort in writing these post-processing scripts. Our proposed code, FP-Tools, is a C++ toolkit designed to help scientists extract and analyze quantities of interest from the output of a molecular dynamics simulation, eliminating the need for them to write these codes themselves and thus reducing this duplication of effort. The quantities which are computed by our code are well documented in the literature (either in publications or textbooks), and the algorithms we implement to compute these properties are also well known in the field. We are not introducing new science or methods here; rather, our primary goal is to provide a useful tool to the community in the form of a well-documented, easy to use package.
As computational models scale to larger computers, the rate at which they produce data has far outstripped the same computers ability to write that data and further the file systems ability to store that data. Almost all of the SciDAC applications, but especially those related to fusion solve very large scale PDEs whose scientific output his impacted by this problem. To gain access to dynamics in an exascale simulation that are not identifiable a priori and to make that dynamical data available to machine learning requires fundamental research in the area of in situ data data analytics. Here data analytics includes compression, visualization, uncertainty quantification, and machine learning. This in situ data analytics will enable on-the-fly spatial and temporal compression of solution dynamics, expose that space-time compressed field to machine learning algorithms that have been specialized to work with dynamically evolving data (existing machine learning algorithms treat data sets as static), greatly improving the opportunity for machine learning to provide feedback to the compression, all within an ongoing simulation, without the need to write data to files. The same concepts are also being applied to uncertainty quantification and multi-fidelity modeling which have similar needs for spatial and temporal compression of the ongoing exascale simulation to perform either without the typical, unacceptable writing of data to files.