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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

High-Throughput Custom Monitoring for the Mu2e TDAQ System

In this project we are studying the application of programmable network hardware to provide a custom monitoring capability for the Mu2e Trigger and Data Acquisition System (TDAQ) system. The goal of the Mu2e experiment is to search for a charged-lepton flavor violating processes where a negative muon converts into an electron in the field of an aluminum nucleus. This experiment is intended to improve by four orders of magnitude the search sensitivity reached so far. We have a working prototype of a system that provides high-throughput, custom monitoring for the Mu2e TDAQ system. The custom Mu2e network packet header format is parsed as it crosses the network switch. Parsing extracts bits that convey information about error states at read-out controllers (ROCs). This information is periodically relayed to the switch controller, which in turn alerts experiment operators.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Synthesis and Characterization of Superconductor Diodes

In the era of modern computing, quantum bits (or qubits) are extensively researched due to their ability to perform computations exponentially faster than classical computers. One promising method for synthesizing qubits on a macroscopic scale is through superconductor diodes (SDs). Unfortunately, SDs are currently limited by their dependence on extremely low temperatures (T ≈ 0K), which restricts their practical usability at larger scales. To address this limitation, researchers are exploring new materials and methods to identify superconductors with higher critical temperatures. My research at the Lawrence Livermore National Laboratory (LLNL) focuses on synthesizing and characterizing superconductor diodes to determine their efficiency for quantum computing applications. Bismuth thin films were synthesized with magnetron sputtering with separate thicknesses which provides information on methods to alter their resistivity. Bismuth was characterized as the topological insulator used in the diode, and its resistivity was measured using a standard four-point probe technique with 1 mA current. Bismuth (99.99% pure) was then purified in a tubular furnace at 400C to use within a Josephson junction as a topological insulator. Niobium and Tantalum Josephson junctions were then synthesized, and they were characterized using a lock-in amplifier four-point probe technique. Materials such as niobium and tantalum are used in high-entropy alloy research, which is a relatively new class of material that has little research within the superconductor diode community, yet the current research shows promise. We anticipate that testing high-entropy superconductors will reveal crucial factors, potentially leading to the development of high-temperature superconductors in the future.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Shorter function summaries for finite state machine-based high consequence systems using logic synthesis and tautologies (Final Report LDRD 24-1302)

Computer programs are often viewed as collections of functions – each function has parameters (inputs) and computes a return value, and each has potential side effects that modify program state (outputs). In this research, a Sandia symbolic execution tool designed to support “human-in-the-loop” analysis was modified to automatically create “function summaries,” and a new tool, “diaboolical,” was created to support enhancing readability of the summary using a novel approach to bit-vector simplification that leverages logic synthesis and tautologies. For this effort, students at Auburn University created several finite state machines (FSMs) to serve as exemplars for high-consequence systems. Function summaries for each of the machines were obtained, and then portions of the summaries were simplified using both diaboolical and the simplification procedure of a popular SMT solver. A comparison of the results shows that diaboolical can often produce smaller function summaries, with expression length improvements over the unsimplified function summaries ranging from 0% to 90% for diaboolical and 0% to 65% for the SMT solver, though diaboolical had a significantly greater cost in time. Diaboolical was evaluated against a collection of “arbitrary” C-code as well as FSM exemplars, and for both datasets it achieved an approximately 10% improvement in expression length compared to simplifications that could be obtained using existing techniques. Function summaries can assist assurance efforts that evaluate existing systems and their executable code. A smaller function summary is likely easier for humans to understand and could thus increase the ability and efficacy of assurance practices centered around the analysis of executable artifacts.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

FY24 Progress Report: SRNL Analysis of ICCWR LCM and WAMS data for Corrosion and Cracking

Algorithms for Machine Learning (ML) and data analysis for the 3013 Surveillance Program have been developed in an ongoing collaborative effort by the Savannah River National Laboratory (SRNL) and the University of South Carolina (USC). The objective of the algorithms is to automate the identification of corrosion and crack formation in the Inner Container Closure Weld Region (ICCWR) of the canister system used to store Pu-bearing material. Data for corrosion and cracking is collected from large binary files generated by a Laser Confocal Microscope (LCM), the Wide Area 3D Measurement System (WAMS), or,in a recent proposal, by a Scanning Electron Microscope (SEM). The ML software uses the physical attributes in the data files (e.g., one or more of: height, color, and 16-bit grayscale values as functions of position in a plane projection) to detect signs of surface corrosion and cracking after being trained on similar data, with the features to be detected. Although the initial scope included screening for broader indicators of corrosion, e.g., pitting, identification of potential cracks was prioritized for the past several years at the request of program leadership. Labeled training data is essential to developing the ML algorithm, and enhancements to data labeling capability have been developed to address this essential precursor to application of ML routines. Efficient labeling is particularly important in view of the large volume of data required to train ML algorithms and the relative rarity of cracks in the ICCWR data set. The updated program will read binary data from either LCM, WAMS or SEM files, interrogate data attributes, facilitate user labeling of data for training ML algorithms, execute ML algorithms, output parameters from trained ML algorithms, report ML model accuracy with respect to labeled data, and generate graphical representations for various analyses. In FY24, hourglass neural networks (HNNs) that were initiated in FY22 were further developed and tested using available LCM data, and their performance was tested against that of the alternative U-Net Neural Network algorithm structure. HNNs along with previously developed Convolutional Neural Networks (CNNs) and Deep Neural Networks (DNNs) comprise a suite of ML tools for identification of cracks in the ICCWR

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗
DOE OSTI2024

Metal Scrap Upcycling with Shear Assisted Processing and Extrusion (ShAPE)

The overarching objective of this project is to convert metal scraps, such as aluminum, titanium, and other alloys provided by the industry, into extruded tubing, wires, and rods. Upcycling of scrap will be accomplished using Shear Assisted Processing and Extrusion (ShAPE). This approach is a new solution for recycling. The specific aims of this project are as follows: 1. Receive metal scrap under a Material Transfer Agreement (MTA), in the form of billets, from select industry partners that meet the following requirements: outer diameter of 1.245 inches (+/-0.003 inches), inner diameter drilled with a 0.404-inch drill bit, and a length of 4.0 inches (+/-0.01 inches). The billet must be cast or compacted to greater than 98% density. If the industry partner does not have the capabilities to prepare the billets, PNNL can make introductions to third-party entities as needed. Industry partners will also provide a composition analysis as weight percent. 2. Extrude metal scrap via the ShAPE process at PNNL. 3. Evaluate and benchmark the extrudate material properties per the ASTM B557-15 – Testing Tubulars Standard or similar wire and rod standards. 4. Characterize the extrudate microstructure for any of the following: grain size, second phase composition, and texture. Additional testing may include corrosion per the ASTM B117 standard and electro-potential. 5. Deliver specimens to industry partners under an MTA for additional third-party evaluations. Industry partners will, in return, provide a non-proprietary report on any testing, including testing per the ASTM B557-15, ASTM B117, and other industry standards. 6. PNNL will develop data and insights to support intellectual property capture, a published non-proprietary technical report, research collaborations, and commercialization opportunities.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗
DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗
DOE OSTI2024

Characterization of throughput on the AXI DMA bus for burst data transfer over Ethernet

cThe Xilinx AXI Direct Memory Access (AXI DMA) module is an efficient solution for medium-speed data transfer in Xilinx SoC FPGAs, supporting data rates greater than 1000 Gbps even in very suboptimal operating modes. It facilitates direct transfer of AXI stream data into processor memory without constant software intervention, which reduces overhead and ensures consistent data logging. By utilizing the FPGA's available memory, large circular buffers (1-5 GiB) are used to buffer data and accommodate network limitations, enabling high-rate data bursts. In this study, we measured the performance of AXI DMA under conditions simulating its lowest practical data transfer speeds. The Arbitrary Length Data Sender was used to transmit AXI stream packets at 32-bit width and 100 MHz frequency, a narrow width and slow speed. Results show that the AXI DMA can transfer up to 3192.76 Mbps with large packet sizes but experiences reduced performance for smaller packets, as low as 2.6 Mbps for 4-byte packets. For Ethernet-limited applications, packet sizes between 8,000 and 16,000 bytes provided optimal transfer speeds of 874 to 1600 Mbps. These findings suggest that the AXI DMA is not the limiting factor in systems where packet sizes exceed 8,000 bytes.

43 PARTICLE ACCELERATORS↗
DOE OSTI2025

Tokamak Disruption Simulation (Final Technical Report)

The Tokamak Disruption Simulation collaboration was a SciDAC (Scientific Discovery through Advanced Computing) program led by Xianzhu Tang of the Los Alamos National Laboratory but with separate grants to each institution. I was the PI for Columbia University and the only person at Columbia directly funded by this SciDAC. Disruptions are a sudden loss of confinement in tokamaks, and a reliable method of preventing disruptions must be developed before tokamak fusion power plants become feasible. A related plasma confinement concept, the stellarator, is the only way known way of preventing disruptions with the required reliability. The largest devices, both existing and under construction, for confining plasmas for fusion using magnetic fields are tokamaks, so it is important to solve their disruption issues. The sudden loss of confinement in tokamaks can be from a bit of material falling into the plasma, which causes the plasma energy to be quickly lost by radiation, or by an instability causing a breakup of the confining surfaces formed by the magnetic field. This breakup can occur more than a million times faster than one would naively think possible. The sudden breakup of surfaces is called a fast magnetic reconnection and also results in a sudden cooling of the plasma.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

LEED: A Lightwave Energy-Efficient Datacenter

The Lightwave Energy-Efficient Datacenter (LEED) program is a disruptive “green-field” approach that provides a quantum leap in the energy efficiency of datacenters. LEED’s fundamental value proposition is that a novel and re-architected optical network—RotorNet— can deliver “more bandwidth per buck” as well as unique system-level attributes that significantly improve overall datacenter energy efficiency and performance. LEED has developed three system-level testbeds. The first testbed uses calibrated hardware and software power measurements to determine server energy efficiency as a function of network bandwidth and workload. These measurements have shown that increasing network communications bandwidth dramatically increases server energy efficiency providing a realistic path to the overall ENLITENED program goal of doubling the number of transactions per joule. The second testbed demonstrates key hardware: a prototype low-loss, high-port count optical “selector switch”. This switch was fabricated, racked, and tested. Measured switch characteristics include loss, bandwidth, crosstalk, switch time, system-level switch time (including the transceivers), and bit error rate. The third testbed demonstrates a fully working and manufactured pinwheel design which dramatically lowers the cost of design, while delivering high switch radix and low reconfiguration times. The LEED project has tied these three novel photonic switch prototypes together with production servers and software through the development of a novel FPGA-based NIC platform called Corundum. Corundum ensures that the packet-switched protocols supported by commodity operating systems and devices can interface with the Rotor switch design. The LEED group has used this combined hardware and software prototype to characterize applications running at a commercially relevant scale. The project has used a combination of enhanced optical modulation amplitude (OMA) modulators, broadband multiplexers and demultiplexers, avalanche photodiodes, and a novel burst-mode receivers to enable the insertion of LEED-developed optical switches without the need for expensive optical amplification. Our modeling has shown that measured LEED-developed device characteristics can achieve link characteristics of 2 pJ/bit including both transceivers and the Rotor switch. In summary, the LEED program has demonstrated a credible and practical path, through novel hardware and software, to realize the program objectives of ENLITENED. The net result will ensure that the United States maintains its strength in the crucial sector of Information Technology, which is vital to both our economic security and our national security.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2025

DIF3D-VARIANT 12.0: Updates and New Features

The DIF3D code has been a workhorse of fast reactor analysis work at Argonne National Laboratory for over 40 years. In 1995, a transport option called VARIANT was added to DIF3D to improve the flux solutions for fast reactor problems which we term DIF3D-VARIANT today. DIF3D-VARIANT performs nodal neutron transport calculations using P N or SP N theory in Cartesian and hexagonal two- and three-dimensional geometries. The limited computing capabilities of the time restricted DIF3D-VARIANT to use at most a 6 th order spatial approximation combined with a P3 flux approximation and P1 scattering kernel for a 33 group structure on most studied reactor problems. Computer capabilities have increased steadily since 1995 and today much larger space-angle-energy approximations are possible. This manuscript serves as an update to the theory section of the original DIF3D-VARIANT manual and details more than twenty years of changes made to DIF3D to make version 12 which was released on November 1 st , 2024. The primary focus of the initial work was to extend the space-angle approximations available in DIF3D-VARIANT such that the error due to transport approximations could be better understood. This work was started and completed in 2002 and marked the official version 10. Unfortunately, those higher order approximations could not be used at that time due to the memory constraints of the BPOINTER part of DIF3D (limited to 2 GB). In version 11, completed in 2012, BPOINTER was circumvented in DIF3D-VARIANT for the largest arrays by introducing a Fortran 90 module called LMA (Large Memory Array). This seamlessly replaces all of the functionality of the BPOINTER concept, but it allows 64 bit addressing for every array such that they can be larger than 2 GB. It is now common for DIF3D-VARIANT jobs to consume 50 GB of memory on modern workstations when using high order space-angle approximations and a large number of groups. Many improvements were made to version 11 from 2012 to 2022 when work to create version 12 started. For version 12, several parts of DIF3D were updated to improve performance and thread parallelism was introduced to further reduce the runtime. Numerous minor bugs were discovered in DIF3D-VARIANT as part of the process of creating the perturbation and sensitivity code PERSENT. All of these algorithmic problems were identified in the transition from version 10 to version 11 which prevented DIF3D-VARIANT from running efficiently and reliably. Firstly, the coarse mesh rebalance scheme would routinely diverge and a study detailed in this report demonstrates how it was also typically not effective. This is not a failure of the coarse mesh rebalance methodology, but a failure of its implementation in DIF3D-VARIANT for hexagonal geometries. The fission source extrapolation algorithm was also found to be unreliable on larger group structure problems, leading to divergence in some cases and a negligible improvement in performance overall. Finally, the “Omega” acceleration applied to the partial current solver routine of DIF3D-VARIANT was found to cause DIF3D-VARIANT to converge to the wrong answer. To resolve these issues, both the coarse mesh rebalance and fission source extrapolation were permanently disabled in version 11. The Tchebychev acceleration was put in as a temporary reliable alternative but it is generally inferior to coarse mesh rebalance or coarse mesh finite difference. For the Omega acceleration, the factor was restricted to guarantee that it would not cause follow-on errors in PERSENT. Due to limited funding to support maintenance and development of DIF3D in the last 10 years, no effort was spent since to resolve the outer iteration acceleration. Except for the threading work, all of the changes discussed in this manuscript refer to changes made between version 10 and version 11. Performance comparisons are done to demonstrate the improvements from version 9 to version 12. As will be demonstrated, the updated versi

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2025

Performance and automatic calibration scheme of the waveform sampler in the ETROC2 ASIC chip

The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge injection test data. After calibration, the baseline random error is reduced by a factor of 2.5–3 compared to the default calibration, and a 5% charge measurement precision is achieved in 15 fC charge injection tests.

Fu, Tao [Unlisted, US]↗
DOE OSTI2025

Ultra-Low Disorder Graphene Quantum Dot-Based Spin Qubits for Cyber Secure Fossil Energy Infrastructure (Final Technical Report)

The overarching goal of the proposed project is to demonstrate the feasibility of creating ultralow local disorder graphene quantum dots (GQDs)-based high-speed, high-fidelity spin quantum bits (qubits) for extremely cyber-secure coal energy plants of the future. Despite their inherent benefits, the coherence times in the state-of-the-art GQD qubits are still low primarily due to the local disorder in GQD devices generated during lithographic fabrication of GQDs. Hence, the focus of this research is to prepare ultralow disorder GQDs (e.g., edge roughness ~0.5nm) and evaluate the low temperature (~mK) charge/spin transport characteristics of the engineered GQD qubit platform. To achieve minimal disorder in GQD qubits, we employ a novel approach that combines nanotomy (novel GQD fabrication technique developed by the PI) and scanning probe microscopy-atomic oxidation lithography (SPM-AOL).

20 FOSSIL-FUELED POWER PLANTS↗
DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗
DOE OSTI2025

Increasing Radon Daughter Plate-out onto Superconducting Qubits

Radon daughter plate-out may pose a fundamental limitation to realizing large-scale superconducting quantum computers. Radon daughters plated-out onto a superconducting qubit chip can decay, releasing energy into the substrate, producing phonons. Phonon induced quasiparticles generate bit flip errors and reduce coherence times. We seek to increase plate-out on chips to enable future study of the impact of Radon on coherence times. In this project, we utilize COMSOL Multiphysics simulations to finalize design for a device to increase radon plate-out.

Kay, Dax [Northwestern U.]↗
DOE OSTI2025

ComStock Measure Documentation: Heat Pump Rooftop Units with Standard Performance

This documentation focuses on a single end-use savings shape measure - heat pump rooftop units (HP-RTUs) with standard efficiencies that are prevalent in the current market. Today, these products are claimed as standard efficiency by the manufacturers and are most commonly installed. This document will primarily discuss the additional changes of performance and configuration of the standard efficiency HP-RTUs while a comprehensive overview of the fundamental modeling methodology and background of the HP-RTU measure, including applicability, sizing scheme, and other key assumptions can be found in the original documentation: Heat Pump RTU. The definition of "standard efficiency" can be a bit vague when considering detailed specifics other than efficiency metrics of a heat pump. Thus, we have focused on reflecting products where manufacturers claim as standard efficiency and products that are not top-of-the-line in their model lineup. Based on gathering information from eight products from four major manufacturers, there are some common (or relatively prevalent) characteristics and we have defined standard efficiency product as follows: direct drive outdoor unit fan, two stages of heat pump cooling, single stage heat pump heating (i.e., all compressors running at the same time), heat pump minimum lockout temperature of 0°F (-17.8°C), backup electric resistance heating, backup heating runs at the same time as heat pump heating , heat pump heating locking out below minimum operating temperature, IEER in between 11-13, and HSPF in between 8-8.9. There are cases where some of these products have other variations: a variable frequency drive fan, dual fuel (i.e., gas backup heating) option, three or more cooling stages, two stages of heat pump heating, no backup heating as default , etc. However, this work tried to reflect the most common and prevalent options for a standard efficiency product.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2025

FY25 Progress Report: SRNL Analysis of ICCWR LCM and WAMS data for Corrosion and Cracking

Algorithms for Machine Learning (ML) and image analysis for the 3013 Surveillance Program have been developed in an ongoing collaborative effort by the Savannah River National Laboratory (SRNL) and the University of South Carolina (USC). The objective of the algorithms is to automate the identification of corrosion and cracks in the Inner Container Closure Weld Region (ICCWR) of the canister system used to store Pu-bearing material. Data for corrosion and cracking is collected from large binary files generated by a Laser Confocal Microscope (LCM), the Wide Area 3D Measurement System (WAMS), or, in a recent proposal, by a Scanning Electron Microscope (SEM). The ML software uses the physical attributes in the data files (e.g., one or more of: height, color, and 16-bit grayscale values as functions of position in a plane projection) to detect signs of surface corrosion and cracking after being trained on similar data with the features to be detected. Although the initial scope included screening for broader indicators of corrosion, e.g., pitting, the identification of potential cracks was prioritized for the past several years at the request of program leadership.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗
DOE OSTI2025

Surrogate Neural Architecture Codesign Package (SNAC-Pack)

Neural Architecture Search is a powerful approach for automating model design, but existing methods struggle to accurately optimize for real hardware performance, often relying on proxy metrics such as bit operations. We present Surrogate Neural Architecture Codesign Package (SNAC-Pack), an integrated framework that automates the discovery and optimization of neural networks focusing on FPGA deployment.

Weitz, Jason [UC, San Diego]↗