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At least 163 records · Page 9

The Galileo Spacecraft: A Communications Legacy for Future Space Flight

The Galileo mission to Jupiter has implemented a wide range of telecommunication improvements in response to the loss of it's high gain antenna. Among the communications enhancements that have been made are the use of advanced compression techniques, packetized telemetry, new error correcting codes and algorithms, more efficient modulation, variable transmission data rates, routine ground antenna arraying (even between continents,) extremely sensitive ground receivers, and non-real-time automated data reconstruction. This telecommunications legacy of Galileo will aid in our abillity to conduct a meaningful exploration of the solar system, and beyond, at a reasonable cost.

Galileo↗

NASA's Deep Space Network (DSN) Lunar Exploration Upgrades (DLEU)

In the near future, the National Aeronautics and Space Administration (NASA) will return to the moon beginning the next era of human exploration. NASA’s Space Communications and Navigation (SCaN) program will play a vital role in establishing communications and navigation support to realize the ambitious goals of the Artemis program. SCaN’s overall lunar communications support plan will be covered in a separate 2023 SpaceOps paper: “NASA’s Communications and Navigation Architecture Plans to Support the Return to the Moon and a Sustainable Lunar Presence”. The plan as it currently stands, includes a three-fold approach of lunar relay services, a dedicated set of new ground stations and support through the Deep Space Network (DSN). This paper will have a more granular focus on the DSN and NASA’s plans to upgrade and expand the network to be better suited for human spaceflight on and around the lunar surface. NASA’s Deep Space Network (DSN) will be a critical communications component for the upcoming lunar activities. There will be multiple spacecraft, using different bands, and some of those spacecraft will be transmitting and receiving using multiple bands, requiring DSN support of S-band (2 GHz), X-band (7 GHz up, 8 GHz down), and K-band (22.5 GHz up, 26 GHz down). Since there may be more than one spacecraft in the beamwidth of the DSN antennas, the DSN support will require an extension of the DSN’s capability to support multiple spacecraft using one antenna, expanding it to provide two simultaneous uplinks in the different bands at each antenna. Achieving this requires using new techniques for manufacturing the frequency selective surfaces, called dichroics, which steer the different frequency beams from and to the appropriate transmitting and receiving equipment, along with the addition of a new K-band uplink system. Additionally, due to the relative closeness of the moon from Earth (as opposed to the planetary missions the DSN supports daily), significantly higher data rates on both uplink and downlink are required, specifically up to 20 Mbps on the uplink and 150 Mbps on the downlink, both using Low Density Parity Check (LDPC) error correcting codes. And, again due to the relative closeness of the moon, there is a need for low latency data delivery of the high rate downlink telemetry which requires a change in the current DSN paradigm of delivering higher rate data with higher latency.

deep space network↗

NASA’s Deep Space Network (DSN) Lunar Exploration Upgrades (DLEU)

In the near future, the National Aeronautics and Space Administration (NASA) will returnhumansto the moon beginning the next era of human exploration. NASA’s Space Communications and Navigation (SCaN) program will play a vital role in establishing communications and navigation support to realize the ambitious goals of the Artemis program. SCaN’s overall lunar communications support plan will be covered in a separate 2023 SpaceOps paper: “NASA’s Communications and Navigation Architecture Plans to Support the Return to the Moon and a Sustainable Lunar Presence.” The four-point plan,as it currently stands, includes lunar relay services, a dedicated set of new ground stations, international partner contributions,and supportthrough the Deep Space Network (DSN)and associated upgrades. This paper will have a more granular focus on the DSN and NASA’s plans to upgrade and expand the network to be better suited for human spaceflight on and around the lunar surface. NASA’s Deep Space Network (DSN) will be a critical communications component for the upcoming lunar activities. There will be multiple spacecraft, using different bands, and some of those spacecraft will be transmitting and receiving using multiple bands, requiring DSN support of S-band (2 GHz), X-band (7 GHz up, 8 GHz down), and K-band (22.5 GHz up, 26 GHz down). Since there may be more than one spacecraft in the beamwidth of the DSN antennas, the DSN support will require an extension of the DSN’s capability to support multiple spacecraft using one antenna, expanding it to provide two simultaneous uplinks in the different bands at each antenna. Achieving this requires using new techniques for manufacturing the frequency selective surfaces, called dichroics, which steer the different frequency beams from and to the appropriate transmitting and receiving equipment, along with the addition of a new K-band uplink system. Additionally, due to the relative closeness of the moon from Earth (as opposed to the planetary missionsthe DSN supports daily), significantly higher data rates on both uplink and downlinkare requiredare possible and desirable by the lunar missions, specifically up to 20 Mbps on the uplink and 150 Mbps on the downlink, both using Low Density Parity Check (LDPC) error correcting codes. And, again due to the relative closeness of the moon, there is a need for low latency data delivery of the high rate downlink telemetry which requires a change in the current DSN paradigm of delivering higher rate data with higher latency.

Moon↗

Internal Correction Of Errors In A DRAM

Error-correcting Hamming code built into circuit. A 256 K dynamic random-access memory (DRAM) circuit incorporates Hamming error-correcting code in its layout. Feature provides faster detection and correction of errors at less cost in amount of equipment, operating time, and software. On-chip error-correcting feature also makes new DRAM less susceptible to single-event upsets.

Zoutendyk, John A.↗

Testing of Error-Correcting Sparse Permutation Channel Codes

A computer program performs Monte Carlo direct numerical simulations for testing sparse permutation channel codes, which offer strong error-correction capabilities at high code rates and are considered especially suitable for storage of digital data in holographic and volume memories. A word in a code of this type is characterized by, among other things, a sparseness parameter (M) and a fixed number (K) of 1 or "on" bits in a channel block length of N.

Shcheglov, Kirill, V.↗

Self-dual (48,24;12) codes

Two self-dual (48,24;12) codes are constructed as 6 x 8 matrices whose columns add up to form an extended BCH-Hamming (8,4;4) code and whose rows sum to odd or even parity. The codes constructed have the identical weight structure of the extended quadratic residue code of length 48. Algebraic isomorphisms may exist between pairs of these three codes. However, because of their matrix form, the newly constructed codes are easily correctable for all five-error and many six-error patterns. The first code comes from restricting a binary cyclic (63,18;36) code to a 6 x 7 matrix and then adjoining six dimensions to the extended 6 x 8 matrix. These six dimensions are generated by linear combinations of row permutations of a 6 x 8 matrix of weight 12, whose sums of rows and columns add to one. The second code comes from a slight modification in the parity (eighth) dimension of the Reed-Solomon (8,4;5) code over GF(64). Error correction in both codes uses the row sum parity information to detect errors in the correction algorithm.

Solomon, G.↗

Error control for reliable digital data transmission and storage systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code.

Costello, D. J., Jr.↗

Simplified Correction Of Errors In Reed-Solomon Codes

New decoder realized by simplified pipeline architecture. Simplified procedure for correction of errors and erasures in Reed-Solomon codes expected to result in simpler decoding equipment. Development widens commercial applicability of Reed-Solomon codes, used to correct bursts of errors in digital communication and recording systems. Improved decoder less complex. Made more regular, simple, and suitable for implementation in both VLSI and software.

Truong, T. K.↗

VLSI Design of a Turbo Decoder

A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

Fang, Wai-Chi↗

Coding for reliable satellite communications

This research project was set up to study various kinds of coding techniques for error control in satellite and space communications for NASA Goddard Space Flight Center. During the project period, researchers investigated the following areas: (1) decoding of Reed-Solomon codes in terms of dual basis; (2) concatenated and cascaded error control coding schemes for satellite and space communications; (3) use of hybrid coding schemes (error correction and detection incorporated with retransmission) to improve system reliability and throughput in satellite communications; (4) good codes for simultaneous error correction and error detection, and (5) error control techniques for ring and star networks.

Gaarder, N. T.↗

Augmented burst-error correction for UNICON laser memory

A single-burst-error correction system is described for data stored in the UNICON laser memory. In the proposed system, a long fire code with code length n greater than 16,768 bits was used as an outer code to augment an existing inner shorter fire code for burst error corrections. The inner fire code is a (80,64) code shortened from the (630,614) code, and it is used to correct a single-burst-error on a per-word basis with burst length b less than or equal to 6. The outer code, with b less than or equal to 12, would be used to correct a single-burst-error on a per-page basis, where a page consists of 512 32-bit words. In the proposed system, the encoding and error detection processes are implemented by hardware. A minicomputer, currently used as a UNICON memory management processor, is used on a time-demanding basis for error correction. Based upon existing error statistics, this combination of an inner code and an outer code would enable the UNICON system to obtain a very low error rate in spite of flaws affecting the recorded data.

Lim, R. S.↗

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗

Soft-Decision-Data Reshuffle to Mitigate Pulsed Radio Frequency Interference Impact on Low-Density-Parity-Check Code Performance

This presentation briefly discusses a research effort on mitigation techniques of pulsed radio frequency interference (RFI) on a Low-Density-Parity-Check (LDPC) code. This problem is of considerable interest in the context of providing reliable communications to the space vehicle which might suffer severe degradation due to pulsed RFI sources such as large radars. The LDPC code is one of modern forward-error-correction (FEC) codes which have the decoding performance to approach the Shannon Limit. The LDPC code studied here is the AR4JA (2048, 1024) code recommended by the Consultative Committee for Space Data Systems (CCSDS) and it has been chosen for some spacecraft design. Even though this code is designed as a powerful FEC code in the additive white Gaussian noise channel, simulation data and test results show that the performance of this LDPC decoder is severely degraded when exposed to the pulsed RFI specified in the spacecraft s transponder specifications. An analysis work (through modeling and simulation) has been conducted to evaluate the impact of the pulsed RFI and a few implemental techniques have been investigated to mitigate the pulsed RFI impact by reshuffling the soft-decision-data available at the input of the LDPC decoder. The simulation results show that the LDPC decoding performance of codeword error rate (CWER) under pulsed RFI can be improved up to four orders of magnitude through a simple soft-decision-data reshuffle scheme. This study reveals that an error floor of LDPC decoding performance appears around CWER=1E-4 when the proposed technique is applied to mitigate the pulsed RFI impact. The mechanism causing this error floor remains unknown, further investigation is necessary.

Ni, Jianjun David↗

Simplified Decoding of Convolutional Codes

Some complicated intermediate steps shortened or eliminated. Decoding of convolutional error-correcting digital codes simplified by new errortrellis syndrome technique. In new technique, syndrome vector not computed. Instead, advantage taken of newly-derived mathematical identities simplify decision tree, folding it back on itself into form called "error trellis." This trellis graph of all path solutions of syndrome equations. Each path through trellis corresponds to specific set of decisions as to received digits. Existing decoding algorithms combined with new mathematical identities reduce number of combinations of errors considered and enable computation of correction vector directly from data and check bits as received.

Truong, T. K.↗