Real-time speech analyzer
System uses phase-locked loops to give real-time information on speech spectrum by tracking the fundamental and its first 19 harmonics.
Hong, J. P.↗
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Low cost omega navigation receiver
The development of a low cost Omega navigation receiver is discussed. Emphasis is placed on the completion and testing of a modular, multipurpose Omega receiver which utilizes a digital memory-aided, phase-locked loop to provide phase measurement data to a variety of applications interfaces. The functional units contained in the prototype device are described. The receiver is capable of receiving and storing phase measurements for up to eight Omega signals and computes two switch-selectable lines of position, displaying this navigation data in chart-recorded form.
Lilley, R. W.↗
Computer program CORDET
A FORTRAN 4 computer program provides convenient simulation of an all-digital phase-lock loop (DPLL). The DPLL forms the heart of the Omega navigation receiver prototype. Through the DPLL, the phase of the 10.2 KHz Omega signal is estimated when the true signal phase is contaminated with noise. This investigation has provided a convenient means of evaluating loop performance in a variety of noise environments, and has proved to be a useful tool for evaluating design changes. The goals of the simulation are to: (1) analyze the circuit on a bit-by-bit level in order to evaluate the overall design; (2) see easily the effects of proposed design changes prior to actual breadboarding; and (3) determine the optimum integration time for the DPLL in an environment typical of general aviation conditions.
Palkovic, R. A.↗
A simulation analysis of phase processing circuitry in the Ohio University Omega receiver prototype
A FORTRAN IV simulation study of the all-digital phase-processing circuitry is described. A digital phase-lock loop (DPLL) forms the heart of the Omega navigation receiver prototype, and through the DPLL, the phase of the 10.2 KHz Omega signal was estimated when the true signal phase is contaminated with noise. The DPLL uses a frequency synthesizer as the reference oscillator. The synthesizer is composed of synchronous rate multipliers (SRM's) driven by a temperature-compensated crystal oscillator, and the use of the SRM's in this application introduces phase jitter which degrades system performance. Simulation of the frequency synthesizer discussed was to analyze the circuits on a bit-by-bit level in order to evaluate the overall design, to see easily the effects of proposed design changes prior to actual breadboarding, to determine the optimum integration time for the DPLL in an environment typical of general aviation conditions, and to quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.
Palkovic, R. A.↗
Synthesis and evaluation of phase detectors for active bit synchronizers
Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.
Mcbride, A. L.↗
Binary processing and display concepts for low-cost Omega receivers
A description is given of concepts related to plans for developing a low-cost, all-digital Omega receiver capable of offering to the small-aircraft pilot a reliable and accurate navigation aid. The receiver base considered includes a receiver front-end module, a receiver control module, a memory-aided phase-locked loop module, a housekeeping timer module, and a synthesizer module.
Lilley, R. W.↗
Electronic circuits
Twenty-nine circuits and circuit techniques developed for communications and instrumentation technology are described. Topics include pulse-code modulation, phase-locked loops, data coding, data recording, detection circuits, logic circuits, oscillators, and amplifiers.
Source record↗
Coordinated design of coding and modulation systems
Work on partial unit memory codes continued; it was shown that for a given virtual state complexity, the maximum free distance over the class of all convolutional codes is achieved within the class of unit memory codes. The effect of phase-lock loop (PLL) tracking error on coding system performance was studied by using the channel cut-off rate as the measure of quality of a modulation system. Optimum modulation signal sets for a non-white Gaussian channel considered an heuristic selection rule based on a water-filling argument. The use of error correcting codes to perform data compression by the technique of syndrome source coding was researched and a weight-and-error-locations scheme was developed that is closely related to LDSC coding.
Massey, J. L.↗
Linear minimum variance filters applied to carrier tracking
A new approach is taken to the problem of tracking a fixed amplitude signal with a Brownian-motion phase process. Classically, a first-order phase-lock loop (PLL) is used; here, the problem is treated via estimation of the quadrature signal components. In this space, the state dynamics are linear with white multiplicative noise. Therefore, linear minimum-variance filters, which have a particularly simple mechanization, are suggested. The resulting error dynamics are linear at any signal/noise ratio, unlike the classical PLL. During synchronization, and above threshold, this filter with constant gains degrades by 3 per cent in output rms phase error with respect to the classical loop. However, up to 80 per cent of the maximum possible noise improvement is obtained below threshold, where the classical loop is nonoptimum, as demonstrated by a Monte Carlo analysis. Filter mechanizations are presented for both carrier and baseband operation.
Gustafson, D. E.↗
Analysis of bilinear noise models in circuits and devices
There are a number of applications in which linear noise models are inappropriate. In the paper, the use of bilinear noise models in circuits and devices is considered. Several physical problems are studied in this framework. These include circuits involving varying parameters (such as variable resistance circuits constructed using field-effect transistors), the effect of switching jitter on sampled data system performance and communication systems involving voltage-controlled oscillators and phase-lock loops. In addition, several types of analytical techniques for stochastic bilinear systems are considered. Specifically, the moment equations of Brockett for bilinear systems driven by white noise are discussed, and closed-form expressions for certain bilinear systems (those that evolve an Abelian or solvable Lie groups) driven by white or colored noise are derived. In addition, an approximate statistical technique involving the use of harmonic expansions is described.
Willsky, A. S.↗
A decision directed detector for the phase incoherent Gaussian channel
A vector digital signalling scheme is proposed for simultaneous adaptive data transmission and phase estimation. The use of maximum likelihood estimation methods predicts a better performance than the phase-locked loop. The phase estimate is shown to converge to the true value, so that the adaptive nature of the detector effectively achieves phase acquisition and improvement in performance. No separate synchronization interval is required and phase fluctuations can be tracked simultaneously with the transmission of information.
Kazakos, D.↗
Extrasensitive phase-locked-loop circuit
Modified phase-locked loop (PLL) generates clock from incoming data signal. To minimize effects of threshold phase-detector gain variations, the PLL uses a dither oscillator, a dither band-pass filter, and correlator instead of coherent amplitude detector.
Nyiri, E. J.↗
Improved numerical control of oscillator frequency
Numerically-controlled oscillator is key element in phase-locked loop that generates exact frequency and phase of noise-corrupted input signal. Device is applicable to communication and tracking equipment.
Cellier, A.↗
Bit-synchronizer lock detector
Circuit measures phase error that exists in phase-locked loop between clock signal recorded in data on magnetic tape and reconstructed clock signal. Circuit presents error as digital word that can be compared with predetermined threshold to indicate lock status. With simple alterations, circuit can also be used as phase detector.
Huey, D. C.↗
Clock synchronization of a large multiprocessor system in the presence of malicious faults
An interconnection algorithm is presented for achieving clock synchronization in a multiprocessor system. The system is assumed to be maliciously faulty, i.e., some processors are out of synchronization and lie about their clock state to other intragroup or intergroup processors. A phase-locked clock network design is proposed which groups the clocks in the system into diverse clusters. The clusters are then treated as single clock units from the perspective of the network. The algorithm minimizes the number of interconnections while permitting synchronization of large multiprocessor systems controlling time-critical applications such as aircraft, nuclear reactors and industrial processes.
Shin, Kang G.↗
Design Concept for a Rapid Automatic Sync Acquisition System
A design has been conceived for a system intended to provide rapid command sync acquisition between widely separated transmitter-receivers, such as between a spacecraft telemetry transmitter, and a ground-based receiver. Use of the system in commercial satellite communications would facilitate rapid sync acquisition between stations and regaining of data lock after interruption or equipment failure. The system is based on a rapid, automatic range-adjustment approach rather than the time-consuming cycle slipping or stepping techniques of conventional phase-locked loops.
Anderson, T. O.↗
A Long-Range Precision Ranging System
A technique is presented that may be used for precision real-time continuous range measuring at long ranges. The technique uses a carrier that is phase modulated by a pseudo-random binary sequence. The characteristics of the sequence that make it acquirable are discussed. The general form of a receiver capable of tracking the carrier is given and is shown to be a kind of phase-locked loop. A two-loop system capable of tracking a pseudo-random sequence and its clock is given. The combination of the receiver and the sequence tracking system form a ranging receiver. The power division necessary between the carrier and the sidebands is shown to be determined by the noise bandwidths of the two tracking systems. The bandwidths necessary for tracking space probes and Earth satellites are given and some experiments in radar-tracking Earth satellites are described. Based on these experiments, estimates are made of the useful range of such a system in tracking space probes.
Easterling, Mahlon↗
An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA
In TDC testing and timing system implementations, it is often necessary to generate signal pulses with finely adjustable time intervals. In delay cell–based schemes, the adjustment resolution is constrained by the propagation delay of the cells—typically 15–20 ps per step—and is sensitive to temperature and supply voltage variations. This document presents a fully digital approach that uses two vernier clocks, generated by two stages of cascaded phase-locked loops (PLLs) with a slight frequency difference, to achieve adjustable timing intervals through accumulated phase differences. The scheme was validated on two families of low-cost FPGA devices, achieving adjustable step sizes of 0.67 ps and 0.97 ps.
Wu, Jin-yuan [Fermilab] (ORCID:0000000344329521)↗