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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Time Data Sequential Processor /TDSP/ computer program provides preflight predictions for lunar trajectories from injection to impact, and for planetary escape trajectories for up to 100 hours from launch. One of the major options TDSP performs is the determination of tracking station view periods.
In pursuit of real time animation of computer simulated space plasma phenomena, the code was rewritten for the Massively Parallel Processor (MPP). The program creates a dynamic representation of the global bowshock which is based on actual spacecraft data and designed for three dimensional graphic output. This output consists of time slice sequences which make up the frames of the animation. With the MPP, 16384, 512 or 4 frames can be calculated simultaneously depending upon which characteristic is being computed. The run time was greatly reduced which promotes the rapid sequence of images and makes real time animation a foreseeable goal. The addition of more complex phenomenology in the constructed computer images is now possible and work proceeds to generate these images.
A finite-volume scheme for numerical integration of the Euler equations was extended to allow solution of the thin-layer Navier-Stokes equations in two and three dimensions. The extended algorithm, which is based on a class of four-stage Runge-Kutta time-stepping schemes, was made numerically efficient through the following convergence acceleration technique: (1) local time stepping, (2) enthalpy damping, and (3) residual smoothing. Also, the high degree of vectorization possible with the algorithm has yielded an efficient program for vector processors. The scheme was evaluated by solving laminar and turbulent flows. Numerical results have compared well with either theoretical or other numerical solutions and/or experimental data.
An integrated system approach to dynamic resource allocation is proposed. Some of the problems in dynamic resource allocation and the relationship of these problems to system structures are examined. A general dynamic resource allocation scheme is presented. A hierarchial system architecture which dynamically maps between processor structure and programs at multiple levels of instantiations is described. Simulation experiments were conducted to study dynamic resource allocation on the proposed system. Preliminary evaluation based on simple dynamic resource allocation algorithms indicates that with the proposed system approach, the complexity of dynamic resource management could be significantly reduced while achieving reasonable effective dynamic resource allocation.
The purpose is to document research to develop strategies for concurrent processing of complex algorithms in data driven architectures. The problem domain consists of decision-free algorithms having large-grained, computationally complex primitive operations. Such are often found in signal processing and control applications. The anticipated multiprocessor environment is a data flow architecture containing between two and twenty computing elements. Each computing element is a processor having local program memory, and which communicates with a common global data memory. A new graph theoretic model called ATAMM which establishes rules for relating a decomposed algorithm to its execution in a data flow architecture is presented. The ATAMM model is used to determine strategies to achieve optimum time performance and to develop a system diagnostic software tool. In addition, preliminary work on a new multiprocessor operating system based on the ATAMM specifications is described.
EAC computer program designed for analysis of errors in results of STAGS computer program (COSMIC Program HQN-10967). Requires input data for geometry of plate, properties of material, and set of boundary conditions. These input data come from STAGS code. (The specific link between input and output data from STAGS and input data for EAC is POSTP, postprocessor program in STAGS processors.) EAC computes continuous solution from discrete results of STAGS in order to estimate error of results of STAGS. Written in FORTRAN 77.
Investigated here is this mapping problem: assign the tasks of a parallel program to the processors of a parallel computer such that the execution time is minimized. First, a taxonomy of objective functions and heuristics used to solve the mapping problem is presented. Next, we develop a highly parallel heuristic mapping algorithm, called Cyclic Pairwise Exchange (CPE), and discuss its place in the taxonomy. CPE uses local pairwise exchanges of processor assignments to iteratively improve an initial mapping. A variety of initial mapping schemes are tested and recursive spectral bipartitioning (RSB) followed by CPE is shown to result in the best mappings. For the test cases studied here, problems arising in computational fluid dynamics and structural mechanics on unstructured triangular and tetrahedral meshes, RSB and CPE outperform methods based on simulated annealing. Much less time is required to do the mapping and the results obtained are better. Compared with random and naive mappings, RSB and CPE reduce the communication time two fold for the test problems used. Finally, we use CPE in two applications on a CM-2. The first application is a data parallel mesh-vertex upwind finite volume scheme for solving the Euler equations on 2-D triangular unstructured meshes. CPE is used to map grid points to processors. The performance of this code is compared with a similar code on a Cray-YMP and an Intel iPSC/860. The second application is parallel sparse matrix-vector multiplication used in the iterative solution of large sparse linear systems of equations. We map rows of the matrix to processors and use an inner-product based matrix-vector multiplication. We demonstrate that this method is an order of magnitude faster than methods based on scan operations for our test cases.
The design and capabilities of two digital controller systems for aeroelastic wind-tunnel models are described. The first allowed control of flutter while performing roll maneuvers with wing load control as well as coordinating the acquisition, storage, and transfer of data for on-line analysis. This system, which employs several digital signal multi-processor (DSP) boards programmed in high-level software languages, is housed in a SUN Workstation environment. A second DCS provides a measure of wind-tunnel safety by functioning as a trip system during testing in the case of high model dynamic response or in case the first DCS fails. The second DCS uses National Instruments LabVIEW Software and Hardware within a Macintosh environment.
A functional schematic, including mass and energy balance, of a solid waste processing system for a controlled ecological life support system (CELSS) was developed using Aspen Plus, a commercial computer simulation program. The primary processor in this system is an incinerator for oxidizing organic wastes. The major products derived from the incinerator are carbon dioxide and water, which can be recycled to a crop growth chamber (CGC) for food production. The majority of soluble inorganics are extracted or leached from the inedible biomass before they reach the incinerator, so that they can be returned directly to the CGC and reused as nutrients. The heat derived from combustion of organic compounds in the incinerator was used for phase-change water purification. The waste streams treated by the incinerator system conceptualized in this work are inedible biomass from a CGC, human urine (including urinal flush water) and feces, humidity condensate, shower water, and trash. It is estimated that the theoretical minimum surface area required for the radiator to reject the unusable heat output from this system would be 0.72 sq m/person at 298 K.
The Gordon Bell Prize recognizes significant achievements in the application of supercomputers to scientific and engineering problems. In 1993, finalists were named for work in three categories: (1) Performance, which recognizes those who solved a real problem in the quickest elapsed time. (2) Price/performance, which encourages the development of cost-effective supercomputing. (3) Compiler-generated speedup, which measures how well compiler writers are facilitating the programming of parallel processors. The winners were announced November 17 at the Supercomputing 93 conference in Portland, Oregon. Gordon Bell, an independent consultant in Los Altos, California, is sponsoring $2,000 in prizes each year for 10 years to promote practical parallel processing research. This is the sixth year of the prize, which Computer administers. Something unprecedented in Gordon Bell Prize competition occurred this year: A computer manufacturer was singled out for recognition. Nine entries reporting results obtained on the Cray C90 were received, seven of the submissions orchestrated by Cray Research. Although none of these entries showed sufficiently high performance to win outright, the judges were impressed by the breadth of applications that ran well on this machine, all nine running at more than a third of the peak performance of the machine.
Aviation research often relies on real-time, pilot-in-the-loop flight simulation as a means to develop new flight software, flight hardware, or pilot procedures. Often these simulations become so complex that a single processor is incapable of performing the necessary computations within a fixed time-step. Threads are an elegant means to distribute the computational work-load when running on a symmetric multi-processor machine. However, programming with threads often requires operating system specific calls that reduce code portability and maintainability. While a multi-threaded simulation allows a significant increase in the simulation complexity, it also increases the workload of a simulation operator by requiring that the operator determine which models run on which thread. To address these concerns an object-oriented design was implemented in the NASA Langley Standard Real-Time Simulation in C++ (LaSRS++) application framework. The design provides a portable and maintainable means to use threads and also provides a mechanism to automatically load balance the simulation models.
Monitoring the evolution of data structures in parallel and distributed programs, is critical for debugging its semantics and performance. However, the current state-of-art in tracking and presenting data-structure information on parallel and distributed environments is cumbersome and does not scale. In this paper we present a methodology that automatically tracks memory bindings (not the actual contents) of static and dynamic data-structures of message-passing C programs, using PVM. With the help of a number of examples we show that in addition to determining the impact of memory allocation overheads on program performance, graphical views can help in debugging the semantics of program execution. Scalable animations of virtual address bindings of source-level data-structures are used for debugging the semantics of parallel programs across all processors. In conjunction with light-weight core-files, this technique can be used to complement traditional debuggers on single processors. Detailed information (such as data-structure contents), on specific nodes, can be determined using traditional debuggers after the data structure evolution leading to the semantic error is observed graphically.
FEM software available to the Mechanical Systems Analysis and Simulation Branch at Goddard Space Flight Center (GSFC) include: 1) MSC/Nastran; 2) Abaqus; 3) Ansys/Multiphysics; 4) COSMOS/M; 5) 'Home-grown' programs; 6) Pre/post processors such as Patran and FEMAP. This viewgraph presentation provides additional information on MSC/Nastran and Ansys/Multiphysics, and includes screen shots of analyzed equipment, including the Wilkinson Microwave Anistropy Probe, a micro-mirror, a MEMS tunable filter, and a micro-shutter array. The presentation also includes information on the verification of results.
The NASA Glenn Research Center was the major contributor of 2-kW-class ion thruster technology to the Deep Space 1 mission, which was successfully completed in early 2002. Recently, NASA s Office of Space Science awarded approximately $21 million to Glenn to develop higher power xenon ion propulsion systems for large flagship missions such as outer planet explorers and sample return missions. The project, referred to as NASA's Evolutionary Xenon Thruster (NEXT), is a logical follow-on to the ion propulsion system demonstrated on Deep Space 1. The propulsion system power level for NEXT is expected to be as high as 25 kW, incorporating multiple ion thrusters, each capable of being throttled over a 1- to 6-kW power range. To date, engineering model thrusters have been developed, and performance and plume diagnostics are now being documented. The project team-Glenn, the Jet Propulsion Laboratory, General Dynamics, Boeing Electron Dynamic Devices, the Applied Physics Laboratory, the University of Michigan, and Colorado State University-is in the process of developing hardware for a ground demonstration of the NEXT propulsion system, which comprises a xenon feed system, controllers, multiple thrusters, and power processors. The development program also will include life assessments by tests and analyses, single-string tests of ion thrusters and power systems, and finally, multistring thruster system tests in calendar year 2005. In addition, NASA's Office of Space Science selected Glenn to lead the development of a 25-kW xenon thruster to enable NASA to conduct future missions to the outer planets of Jupiter and beyond, under the High Power Electric Propulsion (HiPEP) program. The development of a 100-kW-class ion propulsion system and power conversion systems are critical components to enable future nuclear-electric propulsion systems. In fiscal year 2003, a team composed of Glenn, the Boeing Company, General Dynamics, the Applied Physics Laboratory, the Naval Research Laboratory, the University of Wisconsin, the University of Michigan, and Colorado State University will perform a 6-month study that will result in the design of a 25-kW ion thruster, a propellant feed system, and a power processing architecture. The following 2 years will involve hardware development, wear tests, single-string tests of the thruster-power circuits and the xenon feed system, and subsystem service life analyses. The 2-kW-class ion propulsion technology developed for the Deep Space 1 mission will be used for NASA's discovery mission Dawn, which involves maneuvering a spacecraft to survey the asteroids Ceres and Vesta. The 6-kW-class ion thruster subsystem technology under NEXT is scheduled to be flight ready by calendar year 2006. The less mature 25- kW ion thruster system under HiPEP is expected to be ready for a flight advanced development program in calendar year 2006.
Systems and methods are disclosed for detecting a presence of a person in an area of coverage using radar. A transmitter can transmit radio signals in a first direction in an area of coverage defined by a wall and a floor. A receiver can receive the transmitted radio signals reflected back from the area of coverage. A signal conditioning circuit can process the received radio signals. One or more hardware processors can be programmed to analyze the processed radio signals and detect a presence of a person in the area of coverage based on the analysis. The analysis of the processed signals can be performed in both time and frequency domain. In addition to radar, an input from an infrared sensor can also be used in conjunction with radar based detection.
For the Space Technology 5 mission, which is being developed under NASA's New Millennium Program, a single spacecraft processor will be required to do on-board real-time computations and operations associated with attitude control, up-link and down-link communications, science data processing, solid-state recorder management, power switching and battery charge management, experiment data collection, health and status data collection, etc. Much of the health and status information is in analog form, and each of the analog signals must be routed to the input of an analog-to-digital converter, converted to digital form, and then stored in memory. If the micro-operations of the analog data collection process are implemented in software, the processor may use up a lot of time either waiting for the analog signal to settle, waiting for the analog-to-digital conversion to complete, or servicing a large number of high frequency interrupts. In order to off-load a very busy processor, the collection and digitization of all analog spacecraft health and status data will be done autonomously by a field-programmable gate array that can configure the analog signal chain, control the analog-to-digital converter, and store the converted data in memory.
The D-Wave 2X is the third generation of quantum processing created by D-Wave. NASA (with Google and USRA) and Lockheed Martin (with USC), both own D-Wave systems. Los Alamos National Laboratory (LANL) purchased a D-Wave 2X in November 2015. The D-Wave 2X processor contains (nominally) 1152 quantum bits (or qubits) and is designed to specifically perform quantum annealing, which is a well-known method for finding a global minimum of an optimization problem. This methodology is based on direct execution of a quantum evolution in experimental quantum hardware. While this can be a powerful method for solving particular kinds of problems, it also means that the D-Wave 2X processor is not a general computing processor and cannot be programmed to perform a wide variety of tasks. It is a highly specialized processor, well beyond what NNSA currently thinks of as an “advanced architecture.”A D-Wave is best described as a quantum optimizer. That is, it uses quantum superposition to find the lowest energy state of a system by repeated doses of power and settling stages. The D-Wave produces multiple solutions to any suitably formulated problem, one of which is the lowest energy state solution (global minimum). Mapping problems onto the D-Wave requires defining an objective function to be minimized and then encoding that function in the Hamiltonian of the D-Wave system. The quantum annealing method is then used to find the lowest energy configuration of the Hamiltonian using the current D-Wave Two, two-level, quantum processor. This is not always an easy thing to do, and the D-Wave Two has significant limitations that restrict problem sizes that can be run and algorithmic choices that can be made. Furthermore, as more people are exploring this technology, it has become clear that it is very difficult to come up with general approaches to optimization that can both utilize the D-Wave and that can do better than highly developed algorithms on conventional computers for specific applications. These are all fundamental challenges that must be overcome for the D-Wave, or similar, quantum computing technology to be broadly applicable.
The author addresses the problem of exploiting the parallelism available in a program to efficiently employ the resources of the target machine in the context of building a mapping compiler for a distributed memory parallel machine. He demonstrates the effectiveness of using execution models to select the best mapping technique from among those available for a given program segment on a particular machine. Through analysis of the execution models for several mapping techniques for one class of programs on a linear processor array, it is shown that selecting the best technique for a particular program instance can make a significant difference in performance. On the other hand, the results of benchmarks from a mapping compiler for the Warp systolic array machine show that the execution models considered are accurate enough to select the best mapping technique for a given program.