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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9

An FPGA-based hardware accelerator supporting sensitive sequence homology filtering with profile hidden Markov models

Abstract Background Sequence alignment lies at the heart of genome sequence annotation. While the BLAST suite of alignment tools has long held an important role in alignment-based sequence database search, greater sensitivity is achieved through the use of profile hidden Markov models (pHMMs). Here, we describe an FPGA hardware accelerator, called HAVAC, that targets a key bottleneck step (SSV) in the analysis pipeline of the popular pHMM alignment tool, HMMER. Results The HAVAC kernel calculates the SSV matrix at 1739 GCUPS on a $$\sim$$ ∼ $3000 Xilinx Alveo U50 FPGA accelerator card, $$\sim$$ ∼ 227× faster than the optimized SSV implementation in nhmmer . Accounting for PCI-e data transfer data processing, HAVAC is 65× faster than nhmmer’s SSV with one thread and 35× faster than nhmmer with four threads, and uses $$\sim$$ ∼ 31% the energy of a traditional high end Intel CPU. Conclusions HAVAC demonstrates the potential offered by FPGA hardware accelerators to produce dramatic speed gains in sequence annotation and related bioinformatics applications. Because these computations are performed on a co-processor, the host CPU remains free to simultaneously compute other aspects of the analysis pipeline.

59 BASIC BIOLOGICAL SCIENCES↗

Development of MGMC: A proxy Multi-Group Monte Carlo Particle Transport Application

This document details the development and current state of MGMC: a proxy Multi-Group Monte Carlo transport application. The goal of this work was to develop a light-weight Monte Carlo transport solver that could be easily reconfigured to test parallelization strategies targeting advanced architectures and heterogeneous computing environments. Additionally, MGMC is able to act as a proxy-app for testing the development of algorithms and the integration of other libraries and into Monte Carlo transport codes. MGMC is currently able to run in parallel using OpenMP for CPU threads or CUDA for NVIDIA GPUs. MGMC was also used to investigate the using SYCL for portable parallelization targeting either CPU threads, vender-agnostic GPUs, and ARM chips, detailed in Section II. In the process of developing MGMC, several other C++ libraries have been created with the intent for re-use in future research projects and potential inclusion in production-level codes, detailed in Section III. The physics capabilities in MGMC are detailed in Section IV, code verification is detailed in Section V, and performance results are detailed in Section VI.

97 MATHEMATICS AND COMPUTING↗

UPC++ v1.0 Specification, Revision 2020.10.0

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

SST-GPU: A Scalable SST GPU Component for Performance Modeling and Profiling

Programmable accelerators have become commonplace in modern computing systems. Advances in programming models and the availability of unprecedented amounts of data have created a space for massively parallel accelerators capable of maintaining context for thousands of concurrent threads resident on-chip. These threads are grouped and interleaved on a cycle-by-cycle basis among several massively parallel computing cores. One path for the design of future supercomputers relies on an ability to model the performance of these massively parallel cores at scale. The SST framework has been proven to scale up to run simulations containing tens of thousands of nodes. A previous report described the initial integration of the open-source, execution-driven GPU simulator, GPGPU-Sim, into the SST framework. This report discusses the results of the integration and how to use the new GPU component in SST. It also provides examples of what it can be used to analyze and a correlation study showing how closely the execution matches that of a Nvidia V100 GPU when running kernels and mini-apps.

97 MATHEMATICS AND COMPUTING↗

UPC++ v1.0 Specification, Revision 2021.9.0

UPC++ is a C++ library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

Tritium Producing Burnable Absorber Rod (TPBAR) Cutterhead Test Report

The Tritium Extraction Facility (TEF) Target Rod Preparation (TRP) Tritium Producing Burnable Absorber Rod (TPBAR) Cutterhead is a specialized remote tubing cutter used to breach TPBARs (approximately 0.381 inch outside diameter x 0.336 inch inside diameter 316 stainless steel tubing). The cutterhead was originally designed by an external engineering firm - RTS Wright Industries. The bearing housing and drive plate, the main drive components, are designed to be fabricated from Nitronic 60, an anti-galling stainless steel, and coated with Dicronite® (Tungsten Disulfide) lubricating coating. These parts have galled after a limited number of cycles, damaging the fine 3.25-32 UN threads which drive the system. In some cases, destructive sectioning is required to remove the failed parts from the cutterhead. Cutterheads have been fabricated by multiple machine shops, with some cutterheads failing very quickly and some lasting more than 1,000 cuts. In 2019, Emery Corporation, now Toner Machining Technologies (TMT) was contracted to fabricate four (4) new complete sets of cutterheads. The newly fabricated cutterheads have not been able to pass the required acceptance test without the bearing housing and drive plate threads galling. TMT has tried multiple sets of Nitronic 60 bearing housing and drive plates; all have galled after less than 10 cuts.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗

UPC++ v1.0 Specification (Rev. 2023.9.0)

UPC++ is a C++ library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

Venado acceptance: results and tips [Slides]

Nvidia compiler support is not available through cray-mpich/compiler wrapper interface. Adjust CMAKE files to use the correct COMPILER_ID in conditionals and explicit variables to package flags. Use pinned host memory in cray-libsci_acc and cublasXt calls. Set a large blockDim for cublasXt calls. Try MPS and/or explicit numactl binding if performance is lackluster. Use CRAY_MALLOPT_OFF=1 if unexpected OOM errors appear using cce. Use MPICH_SMP_SINGLE_COPY_MODE=CMA for xpmem issues. Use MPICH_OPT_THREAD_SYNC=0 for MPI_THREAD issues. Poor CUDA-aware MPI performance remains an issue.

97 MATHEMATICS AND COMPUTING↗

Uncertainty Quantification for Component Modeling Using the Discrete-Direct Approach

Threaded fastener behavior can be an important aspect of complex component and system behavior, but there is no one-size-fits-all finite element analysis technique. Proper modeling of threaded fastener joints requires careful consideration of many details, from test setup and data acquisition to constitutive modeling and uncertainty quantification approaches. This report details analysis of a “mini-radax” bolted-joint exemplar where a Discrete-Direct uncertainty quantification approach is employed to evaluate margin of the component. The mini-radax geometry is tested to failure on a drop table, and single-coupon tests of individual fasteners serve as foundational data for the analysis. Analysis predictions complement the test data well and provide additional context for engineering decision-making.

42 ENGINEERING↗

Correct Compilation of Concurrent C Code

The CompCert compiler represents a landmark effort in program verification as both a piece of verified software and as a compiler for verified C programs. A key shortcoming of CompCert however is that it does not support multithreaded programs. Prior work to add threads to CompCert has either required major rewrites of parts of the proof or only works for well synchronized programs. The problem is that CompCert’s backward simulation derives from a forward simulation via the determinism of the semantics of intermediate representation languages. This makes the proofs in CompCert easier but also makes them incompatible with standard models of multithreading which are non-deterministic. Here we propose an alternate formulation of CompCert’s proof structure that parameterizes the existing single threaded semantics with nondeterministic behavior generated at the multithreading level. While this is an old trick where program equivalence is concerned, performing it in the context of CompCert is quite subtle. Our approach allows for expressive concurrent semantics and does not require major proof rewrites but still results in a global backward simulation for multithreaded programs.

97 MATHEMATICS AND COMPUTING↗

DIF3D-VARIANT 12.0: Updates and New Features

The DIF3D code has been a workhorse of fast reactor analysis work at Argonne National Laboratory for over 40 years. In 1995, a transport option called VARIANT was added to DIF3D to improve the flux solutions for fast reactor problems which we term DIF3D-VARIANT today. DIF3D-VARIANT performs nodal neutron transport calculations using P N or SP N theory in Cartesian and hexagonal two- and three-dimensional geometries. The limited computing capabilities of the time restricted DIF3D-VARIANT to use at most a 6 th order spatial approximation combined with a P3 flux approximation and P1 scattering kernel for a 33 group structure on most studied reactor problems. Computer capabilities have increased steadily since 1995 and today much larger space-angle-energy approximations are possible. This manuscript serves as an update to the theory section of the original DIF3D-VARIANT manual and details more than twenty years of changes made to DIF3D to make version 12 which was released on November 1 st , 2024. The primary focus of the initial work was to extend the space-angle approximations available in DIF3D-VARIANT such that the error due to transport approximations could be better understood. This work was started and completed in 2002 and marked the official version 10. Unfortunately, those higher order approximations could not be used at that time due to the memory constraints of the BPOINTER part of DIF3D (limited to 2 GB). In version 11, completed in 2012, BPOINTER was circumvented in DIF3D-VARIANT for the largest arrays by introducing a Fortran 90 module called LMA (Large Memory Array). This seamlessly replaces all of the functionality of the BPOINTER concept, but it allows 64 bit addressing for every array such that they can be larger than 2 GB. It is now common for DIF3D-VARIANT jobs to consume 50 GB of memory on modern workstations when using high order space-angle approximations and a large number of groups. Many improvements were made to version 11 from 2012 to 2022 when work to create version 12 started. For version 12, several parts of DIF3D were updated to improve performance and thread parallelism was introduced to further reduce the runtime. Numerous minor bugs were discovered in DIF3D-VARIANT as part of the process of creating the perturbation and sensitivity code PERSENT. All of these algorithmic problems were identified in the transition from version 10 to version 11 which prevented DIF3D-VARIANT from running efficiently and reliably. Firstly, the coarse mesh rebalance scheme would routinely diverge and a study detailed in this report demonstrates how it was also typically not effective. This is not a failure of the coarse mesh rebalance methodology, but a failure of its implementation in DIF3D-VARIANT for hexagonal geometries. The fission source extrapolation algorithm was also found to be unreliable on larger group structure problems, leading to divergence in some cases and a negligible improvement in performance overall. Finally, the “Omega” acceleration applied to the partial current solver routine of DIF3D-VARIANT was found to cause DIF3D-VARIANT to converge to the wrong answer. To resolve these issues, both the coarse mesh rebalance and fission source extrapolation were permanently disabled in version 11. The Tchebychev acceleration was put in as a temporary reliable alternative but it is generally inferior to coarse mesh rebalance or coarse mesh finite difference. For the Omega acceleration, the factor was restricted to guarantee that it would not cause follow-on errors in PERSENT. Due to limited funding to support maintenance and development of DIF3D in the last 10 years, no effort was spent since to resolve the outer iteration acceleration. Except for the threading work, all of the changes discussed in this manuscript refer to changes made between version 10 and version 11. Performance comparisons are done to demonstrate the improvements from version 9 to version 12. As will be demonstrated, the updated versi

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

Water-Resistant Container Testing: A426-7, A426-25, and A426-50 Container Designs

The purpose of this report is to detail the results of water ingress testing conducted on the A426-7, A426-25, and A426-50 Mini-Pot container designs and discuss these results against the water-resistant container requirements of TA55-AP-522 and PA-RD-01009. The A426 design series is a proposed commercially off the shelf inner container option for material storage inside of a glovebox and/or as an approved nonhermetically sealed inner of an approved packaging configuration inside of an approved outer container as listed in PA-RD-01022. The A426-25 and A426-50 are shaped similar to an ointment jar, made of 316L stainless steel, and utilize a threaded lid for closure and containment. The A426-7 container is shaped similar to a vial, made of 316L stainless steel, and utilizes a threaded lid for closure and containment. See Figure 1 and Table 1-3 for a summary of the container specifications. For more details on the container design, see Section 1.4.

42 ENGINEERING↗

UPC++ v1.0 Specification (Revision 2022.3.0)

UPC++ is a C++ library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

UPC++ v1.0 Specification, Revision 2023.3.0

UPC++ is a C++ library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

UPC++ v1.0 Specification (Revision 2021.3.0)

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

UPC++ v1.0 Specification, Revision 2022.9.0

UPC++ is a C++ library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

UPC++ v1.0 Specification, Revision 2020.3.0

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

Concurrent conditions access across validity intervals in CMSSW

The CMS software system, known as CMSSW, has a generalized conditions, calibration, and geometry data products system called the EventSetup. The EventSetup caches results of reading or calculating data products based on the 'interval of validity', IOV, which is based on the time period for which that data product is appropriate. With the original single threaded CMSSW framework, updating only on an IOV boundary meant we only required memory for a single data product of a given type at any time during the program execution. In 2016 CMS transitioned to using a multi-threaded framework as away to save on memory during processing. This was accomplished by amortizing the memory cost of EventSetup data products across multiple concurrent events. To initially accomplish that goal required synchronizing event processing across IOV boundaries, thereby decreasing the scalability of the system. In this presentation we will explain how we used 'limited concurrent task queues' to allow concurrent IOVs while still being able to limit the memory utilized.

Dagenhart, David↗