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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. Further, the different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

36 MATERIALS SCIENCE↗
NASA NTRS1999

Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-(micron)meter MOSFET's with Epitaxial and (delta)-Doped Channels

A detailed three-dimensional (3-D) statistical 'atomistic' simulation study of fluctuation-resistant sub-0.1-(micron)meter MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-(micron)meter generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channel. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-(micron)meter devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta-doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-(micron)meter MOSFET's. Index Terms-Doping, fluctuations, MOSFET, semiconductor device simulation, silicon devices, threshold.

Asenov, Asen↗
DOE OSTI2022

Material aspects of giga-Hertz ZnO TFTs for wireless systems

Abstract Having enabled high-value application capabilities through mass production of flat-panel displays, X-ray imagers, and solar panels, Large-Area Electronics (LAE) holds potential to open new frontiers in wireless applications for the Internet of Things and 5G/6G, by enabling unprecedented spatial control and power efficiency through large size and flexible form factor of radiative apertures. However, this requires boosting operation frequencies from the traditional limits in the range of 10–100’s of mega-Hertz to multi giga-Hertz. In this paper, we discuss critical device metrics, to characterize zinc-oxide (ZnO) thin-film transistor (TFT) operation frequency for both active (for signal amplification) and passive components in LAE-based circuits and systems. We then describe the key structural and material approaches towards recently demonstrated LAE-based giga-Hertz wireless systems employing ZnO TFTs. Bringing LAE to the giga-Hertz regime provides a path towards flexible and meter-scale monolithic integrated wireless systems. Graphical abstract

Ma, Yue (ORCID:0000000186724090)↗
DOE OSTI2023

A Smart Silicon Carbide Power Module With Pulse Width Modulation Over Wi-Fi and Wireless Power Transfer-Enabled Gate Driver, Featuring Onboard State of Health Estimator and High-Voltage Scaling Capabilities

A wide range of utility applications require controllable switches with features such as high-voltage blocking and high-current carrying capacity, especially at high pulse width modulation (PWM) frequency. Low- and medium-voltage utility applications such as motor drives and flexible AC transmission systems as well as solid state transformers could also benefit from a low-cost high-voltage switching module. Wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) metal oxide semiconductor field effect transistors (MOSFETs) are considered to be the present and next-generation device choices, although they have limitations. For relatively high-voltage applications with demanding thermal management, SiC is still the only choice, and GaN dominates the low-voltage regime. This manuscript proposes a new half-bridge power MOSFET module that is suitable for conventional H-bridge of multilevel configurations used in high-voltage applications. Constructed from bare SiC dies, this half-bridge module takes advantage of (1) optimized MOSFET placement inside the module, (2) customized heat exchanger, manifold, and cooling, (3) integrated gate driver module with pulse width modulation (PWM) over wi-fi to eliminate the need for low-voltage signals, (4) wireless power transfer (WPT)-enabled gate driver and other ancillary circuits, (5) and the option to incorporate an onboard state-of-health (SOH) estimator module. The entire architecture has been designed and built at the National Renewable Energy Laboratory (NREL) in Golden, CO.

Ga2O3 devices↗
DOE OSTI2024

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

Abstract This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and$$\text {Hf}_{0.5}\text {Zr}_{0.5}\text {O}_2$$ Hf 0.5 Zr 0.5 O 2 (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

Science & Technology - Other Topics↗
NASA NTRS1987

The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

Hsu, I. S.↗
NASA NTRS1994

Nonvolatile programmable neural network synaptic array

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Tawel, Raoul↗
NASA NTRS2016

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

high temperature↗
DOE OSTI2023

Josephson Traveling Wave Parametric Amplifiers to Enable Future Neutrino Mass Measurements

Technologies for “quantum sensing" have the promise of dramatically improved sensitivity in some experiments that explore nuclear physics at the boundaries of our current knowledge. In particular, the Josephson Traveling Wave Parametric Amplifier (JTWPA) could enable future experiments such as Project 8 that use Cyclotron Radiation Emission Spectroscopy (CRES) to measure the absolute neutrino mass scale in tritium beta decays. CRES consists of detecting a signal of approximately one femtowatt of power radiated by electrons trapped in a 1-T magnetic field. The frequency of that radiation, around 27 GHz for a tritium endpoint electron, is inversely proportional to the electron energy. One of the significant challenges of a CRES experiment is the detection of minimal signal power levels. State-of-the-art transistor-based technologies will not likely achieve sufficient signal-to-noise ratio (SNR) in a competitive neutrino mass experiment. However, emerging quantum technologies have been demonstrated to operate at the fundamental lower limits of noise permitted by the laws of quantum mechanics. Of those technologies, JTWPAs appear to satisfy future performance needs with speed gain, bandwidth, and very low noise. We propose to bring together a group of neutrino physicists, experts in the needs of future neutrino mass measurements, with leaders in the field of quantum information science and JTWPA technology to develop JTWPAs appropriate for neutrino mass measurements.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2026

Growth of Low-Defect WSe 2 Film via High-Purity van der Waals Crystal Precursor

Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) exhibit exceptional electrical and optical properties, empowering their promising prospects for future nanoelectronics. Despite major advances in n-type 2D semiconductors, the field has yet to synthesize high-mobility p-type 2D TMDs, in particular WSe 2 , and systematically query the influence of defects. In this study, we unveil the pivotal role of substitutional impurity defects vis-à-vis the precursor used and growth method employed in defining the quality of 2D p-type WSe 2 . Density functional theory calculations suggest the adverse effect of Fe-, Co-, Ni- and Si-substituted W impurity defects on the mobility of WSe 2 , whereas defects such as O-, S-substituted Se and Mo-substituted W pose negligible impact. Guided by the theory, we pinpoint van der Waals (vdW) crystals, commonly used in mechanical exfoliation, as the optimal precursor, and develop a facile vdW crystal physical vapor deposition (PVD) method to grow high-purity monolayer 2D WSe 2 film (VPVD-WSe 2 ) that is continuous across a centimeter scale. A suite of spectroscopies confirms the markedly reduced defect density of the as-synthesized WSe 2 compared to those by typical chemical vapor deposition methods, and by PVD with commercial or hydrothermal precursors. Scanning tunneling microscopy further evidence the ultralow substitutional impurity defect density of VPVD-WSe 2 , greatly outperforming the control samples and approaching the mechanically exfoliated counterparts. The VPVD-WSe 2 based field-effect transistors exhibit notable electrical performance with record-high field-effect hole mobility up to 112 cm 2 V –1 s –1 at room temperature, exceeding the best-reported monolayer WSe 2 synthesized by chemical vapor deposition and rivaling the mechanically exfoliated 2D WSe 2 flakes.

WSe2↗
NASA NTRS2010

N channel JFET based digital logic gate structure

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Krasowski, Michael J.↗
DOE OSTI2025

Magnon spectroscopy in the electron microscope

Abstract The miniaturization of transistors is approaching its limits owing to challenges in heat management and information transfer speed 1 . To overcome these obstacles, emerging technologies such as spintronics 2 are being developed, which make use of the electron’s spin as well as its charge. Local phenomena at interfaces or structural defects will greatly influence the efficiency of spin-based devices, making the ability to study spin-wave propagation at the nanoscale and atomic scale a key challenge 3,4 . The development of high-spatial-resolution tools to investigate spin waves, also called magnons, at relevant length scales is thus essential to understand how their properties are affected by local features. Here we detect bulk THz magnons at the nanoscale using scanning transmission electron microscopy (STEM). By using high-resolution electron energy-loss spectroscopy with hybrid-pixel electron detectors, we overcome the challenges posed by weak signals to map THz magnon excitations in a thin NiO nanocrystal. Advanced inelastic electron scattering simulations corroborate our findings. These results open new avenues for detecting magnons and exploring their dispersions and their modifications arising from nanoscale structural or chemical defects. This marks a milestone in magnonics and presents exciting opportunities for the development of spintronic devices.

Science & Technology - Other Topics↗
DOE OSTI2025

Low Cost High-Performance HRE-Free 3-in-1 Electric Drive Unit

The project team completed work to expand upon American Axle & Manufacturing’s (AAM) baseline technology and develop a high-speed, AC induction electric drive unit (EDU) with total direct-oil-cooling and integrated power electronics. The project accelerated advancements in EDU technology by allowing AAM to build upon the progress made in developing the underlying baseline technologies. The following seven improvements to AAM’s baseline technology were implemented in this research and development program: 1) Increased speed (30k RPM) AC induction motor, 2) Silver-sintering of discrete silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFET) to heat sinks, 3) Electrically insulated rotor bars, 4) Optimized lamination steel, 5) EDU-integrated 650VDC inverter package, 6) Over-molded stator with molded liners, and 7) 650VDC power-dense stator design. The successful development of the technology resulted in a meaningful cost reduction for EDU systems in the market. Coupled with falling battery system costs, lower EDU costs will likely accelerate the market acceptance and related production scaling of battery electric vehicles. The objective of this project was to research, develop, and test a Heavy Rare Earth (HRE)-free 3-In-1 electric drive unit (EDU) that has class leading power density and cost. The key technologies to be developed were anticipated to meet or exceed the Department of Energy (DOE) targets of a cost ≤ $\$$7/kilowatt (kW), power density ≥ 12 kW/liter, and operating voltage ≥ 600 VDC.

33 ADVANCED PROPULSION SYSTEMS↗
NASA NTRS2016

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

Ikpe, Stanley A.↗
NASA NTRS1991

Direct kinematics solution architectures for industrial robot manipulators: Bit-serial versus parallel

A Very Large Scale Integration (VLSI) architecture for robot direct kinematic computation suitable for industrial robot manipulators was investigated. The Denavit-Hartenberg transformations are reviewed to exploit a proper processing element, namely an augmented CORDIC. Specifically, two distinct implementations are elaborated on, such as the bit-serial and parallel. Performance of each scheme is analyzed with respect to the time to compute one location of the end-effector of a 6-links manipulator, and the number of transistors required.

Lee, J.↗
DOE OSTI2022

Thermal Optimization of a Silicon Carbide, Half-Bridge Power Module

This project describes the modeling process to design the packaging and heat exchanger for a half-bridge wide-bandgap (WBG) power semiconductor module. The module uses two silicon carbide, metal-oxide-semiconductor field-effect transistor (MOSFET) devices per switch position that are soldered to an aluminum nitride, direct-bond copper (DBC) substrate. A baseplate cooling configuration (e.g., no thermal grease) is used along with a water-ethylene glycol, jet-impingement-style heat exchanger. The heat exchanger was designed to be fabricated using prototyping equipment from the National Renewable Energy Laboratory, complies with automotive standards (for minimal channel sizes, flow rates, and coolant), and considers reliability aspects (i.e., erosion/corrosion). Device-scale computational fluid dynamics (CFD) is used first to design the slot jet impingement cooling configuration and compute the effective heat transfer coefficient (HTC) of the concept. The computed HTCs are then used as boundary conditions for a finite element study to optimize the package geometry (e.g., device layout and baseplate thickness) to minimize thermal resistance and minimize temperature variation between the module's four devices. Finally, a fluid manifold is designed to generate the slot jets and cool the devices. Module-scale CFD predicts a relatively low junction-to-fluid thermal resistance of 16.7 mm2 K/W, a 1.4 degrees C temperature variation between devices, and a total pressure drop of 5,860 Pa (0.85 psi) for the design. The thermal resistance of the module design is about 67% lower than the 2015 BMW i3 power electronics/modules thermal resistance.

DIRECT ENERGY CONVERSION↗
NASA NTRS2011

Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications Rad-Hard, Miniaturized

A paper discusses the successful development of a miniaturized radiation hardened high-voltage switching module operating at 2.5 kV suitable for space application. The high-voltage architecture was designed, fabricated, and tested using a commercial process that uses a unique combination of 0.25 micrometer CMOS (complementary metal oxide semiconductor) transistors and high-voltage lateral DMOS (diffusion metal oxide semiconductor) device with high breakdown voltage (greater than 650 V). The high-voltage requirements are achieved by stacking a number of DMOS devices within one module, while two modules can be placed in series to achieve higher voltages. Besides the high-voltage requirements, a second generation prototype is currently being developed to provide improved switching capabilities (rise time and fall time for full range of target voltages and currents), the ability to scale the output voltage to a desired value with good accuracy (few percent) up to 10 kV, to cover a wide range of high-voltage applications. In addition, to ensure miniaturization, long life, and high reliability, the assemblies will require intensive high-voltage electrostatic modeling (optimized E-field distribution throughout the module) to complete the proposed packaging approach and test the applicability of using advanced materials in a space-like environment (temperature and pressure) to help prevent potential arcing and corona due to high field regions. Finally, a single-event effect evaluation would have to be performed and single-event mitigation methods implemented at the design and system level or developed to ensure complete radiation hardness of the module.

Adell, Philippe C.↗
DOE OSTI2022

Nondestructive microstructural investigation of defects in 4H-SiC epilayers using a multiscale luminescence analysis approach

The development of metal oxide semiconductor field effect transistors (MOSFETs) utilizing epitaxially grown 4H-SiC has accelerated in recent years due to their favorable properties, including a high breakdown field, high saturated electron drift velocity, and good thermal conductivity. However, extended defects in epitaxial 4H-SiC can affect both device yields and operational lifetime. In this work, we demonstrate the importance of a multiscale luminescence characterization approach to studying nondestructively extended defects in epitaxial 4H-SiC semiconducting materials. Multiscale luminescence analysis reveals different aspects of excess charge carrier recombination behavior based on the scale of a particular measurement. Combining measurements of the same extended defect area at different scales tells us more about the essential nature of that defect and its microstructure. Here, we use photoluminescence imaging and cathodoluminescence spectrum imaging to investigate the recombination behavior of several different types of extended defects, including stacking faults, inclusions, and basal plane dislocations. A detailed understanding of the optoelectronic properties of extended defects in epitaxial SiC helps elucidate the microstructure of extended defects and can provide pathways to mitigate detrimental changes during device operation related to their evolution, such as the recombination enhanced dislocation glide effect that affects SiC-based MOSFETs.

3C-inclusion↗