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DOE OSTI2021

Multilevel Combinatorial Optimization across Quantum Architectures

Emerging quantum processors provide an opportunity to explore new approaches for solving traditional problems in the post Moore’s law supercomputing era. However, the limited number of qubits makes it infeasible to tackle massive real-world datasets directly in the near future, leading to new challenges in utilizing these quantum processors for practical purposes. Furthermore, hybrid quantum-classical algorithms that leverage both quantum and classical types of devices are considered as one of the main strategies to apply quantum computing to large-scale problems. In this article, we advocate the use of multilevel frameworks for combinatorial optimization as a promising general paradigm for designing hybrid quantum-classical algorithms. To demonstrate this approach, we apply this method to two well-known combinatorial optimization problems, namely, the Graph Partitioning Problem, and the Community Detection Problem. We develop hybrid multilevel solvers with quantum local search on D-Wave’s quantum annealer and IBM’s gate-model based quantum processor. We carry out experiments on graphs that are orders of magnitude larger than the current quantum hardware size, and we observe results comparable to state-of-the-art solvers in terms of quality of the solution.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

VTK-m: Visualization for the Exascale Era and Beyond

A recent trend in modern high-performance computing is the increasing use of hybrid architectures, where the vast majority of performance comes from accelerators. Modern accelerators are based on Graphics Processing Units (GPU) that contain many low power cores that in their aggregate provides an extremely high computation rate. Current and future CPU processors are requiring more explicit parallelism as each successive version of the hardware packs in more cores, and technologies like hyperthreading and vector operations require even more parallel processing to leverage each core’s full potential. As an example, the Frontier supercomputer installed at Oak Ridge National Laboratories recently hit a record breaking 1.1 exaflops1 on the LINPACK HPC benchmark [Shoemaker 2022]. The system contains 37632 AMD MI250x GPUs which requires more than half a billion threads to keep the system fully utilized [Khizeran 2022].VTK-m is a toolkit of scientific visualization algorithms for these emerging processor architectures. VTK-m supports the fine-grained concurrency for data analysis and visualization algorithms required to drive extreme scale computing by providing abstract models for data and execution that can be applied to a variety of algorithms across many different processor architectures.

Bolstad, Mark↗

DOE OSTI2024

HamPerf: A Hamiltonian-Oriented Approach to Quantum Benchmarking

Quantum computing technologies are undergoing rapid development. The different qubit modalities being considered for quantum computing each have their strengths and weaknesses, making it challenging to compare their performance relative to each other and the state-of-the-art in classical high-performance computing. To better understand the utility of a given quantum processor and to assess when and how it will be able to advance the frontiers of computational science, researchers need a robust approach to quantum benchmarking. A variety of approaches have been proposed, many of which characterize the presence of noise in current quantum devices. These efforts include component-level performance metrics, such as randomized benchmarking and gate set tomography; high-level application-dependent metrics; and devicelevel metrics, such as the Quantum Volume. However, it remains unclear how low-level metrics, such as fidelities and decoherence times, and global device metrics, such as Quantum Volume, relate to the computational utility and practical limitations of quantum processors to solve useful problems. In this paper, we describe our Hamiltonian-oriented approach to quantum benchmarking called HamPerf. Where previous application-dependent approaches specify a suite of benchmarking circuits inspired by applications, we place the problem Hamiltonian at the center. Our strategy allows us to probe the computational performance of a quantum processor on standardized and relevant problem sets, agnostic of the algorithms and hardware used to solve them; it also provides fundamental insights into how device characteristics correlate with computational utility.

Butko, Anastasiia↗

DOE OSTI2014

Domi

Domi (Greek for "structure") is a Trilinos package that provides support for multi-dimensional data arrays distributed over multiple processors of a high performance computing system. The software supports data arrays of arbitrary number of dimensions mapped to a multi-dimensional grid of processors. Domi provides local access to the data, as well as the ability to compute global quantities such as norms, maxima and minima. Data arrays can be constructed with boundary and communication padding, necessary for finite difference algorithms, and provides high-level methods for communicating data between processors to update these buffers. The distributed maps and vectors in Domi can be converted to the equivalent data structures in Epetra and Tpetra (both of which assume unstructured data), using view semantics when appropriate, for use with other Trilinos solvers.

Spotz, WilliamF.↗

DOE OSTI2018

fftMPI, a library for performing 2d and 3d FFTs in parallel

The fftMPI library enables two and three dimensional Fast Fourier Transforms (FFTs) to be performed efficiently in parallel on a variety of platforms from desktop machines to supercomputers. It allows for flexibility in the initial distribution of the FFT grid across processors, as well as the final output. It handles the data communication and reordering necessary to perform multi-dimensional FFTs in parallel. It relies on open-source or vendor-provided libraries to perform one dimensional FFTs on a single processor. It uses MPI for inter-processor communication, which is a standard distributed memory message-passing library.

Plimpton, Steven↗

DOE OSTI2019

slaclab/smurf-processor-base-docker

This docker image, named smurf-processor-base contains smurf-processor and additional tools used by the SMuRF project. It is based on the smurf-rogue docker image and contains smurf-processor.

Vasquez, Jesus↗

DOE OSTI2018

Strategies for Reducing Moisture Content in Forest Residues at the Harvest Site

Abstract. The moisture content (MC) of biomass derived from forest residues can pose a challenge to biomass utilization. It plays a significant role in determining the cost of transportation and subsequent market price. Additionally, emerging biomass conversion technologies, such as gasification, torrefaction, and briquetting, have very narrow specifications for the MC (e.g., <15%) in their feedstocks. The goal of this study was to develop strategies for reducing moisture content by evaluating different arrangement patterns of forest residues and its effect on MC reduction at the harvest site. The study compared four different arrangement patterns including criss-cross, teepees, traditional piling (processor piled), and scattered residues in three different timber harvest units in northern California. Two of the arrangement patterns (criss-cross and processor piled) were also covered with a plastic cover. Samples were collected from each treatment using a transect method and were recorded for 12 months. There was an overall drop of MC from 52% (freshly cut) to 12% between all arrangements over the study period. The cost of construction per pile, averaged $37, $41, and $48 for teepees, criss-cross, and processor piles, respectively. Even though, there was no significant difference in MC reduction between piles (except scattered), each pile arrangement of forest residues directly affected biomass feedstock operations, logistics, and costs. Keywords: Feedstock quality, Logging slash, Transect sampling method, Woody biomass energy.

Agriculture↗

DOE OSTI2017

Advanced Control Systems for Wave Energy Converters

This submission contains several papers, a final report, descriptions of a theoretical framework for two types of control systems, and descriptions of eight real-time flap load control policies with the objective of assessing the potential improvement of annual average capture efficiency at a reference site on an MHK device developed by Resolute Marine Energy, Inc. (RME). The submission also contains an LCOE model that estimates the performance and related energy cost improvements that each advanced control system might provide and recommendations for improving DOE's LCOE model. The two types of control systems are for wave energy converters which transform data into commands that, in the case of RME's OWSC wave energy converter, provide real-time adjustments to damping forces applied to the prime mover via the power take-off system (PTO). The control theories developed were: 1) Model Predictive Control (MPC) or so-called "non-causal" control whereby sensors deployed seaward of a wave energy converter measure incoming wave characteristics and transmit that information to a data processor which issues commands to the PTO to adjust the damping force to an optimal value; and 2) "Causal" control which utilizes local sensors on the wave energy converter itself to transmit information to a data processor which then issues appropriate commands to the PTO. The two advanced control policies developed by Scruggs and Re Vision were then compared to a simple control policy, Coulomb damping, which was utilized by RME during the two rounds of ocean trials it had conducted prior to the commencement of this project. The project work plan initially included a provision for RME to conduct hardware-in-the-loop (HIL) testing of the data processors and configurations of valves, sensors and rectifiers needed to implement the two advanced control systems developed by Scruggs and Re Vision Consulting but the funding for that aspect of the project was cut at the conclusion of Budget Period 1. Accordingly, more work needs to be done to determine: a) means and feasibility of implementing real-time control; and b) added costs associated with such implementation taking into account estimated effects on system availability in addition to component costs.

16 TIDAL AND WAVE POWER↗

DOE OSTI2018

NEW EPICS/RTEMS IOC BASED ON ALTERA SOC AT JEFFERSON LAB

A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA is being designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 Hard Processor System (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via U-Boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDR3 SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-Boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run RTEMS and EPICS. The first design of the SoC IOC will be compatible with Jefferson Lab’s current PC104 IOCs, which have been running in CEBAF 10 years. The next design would be mounting in a chassis and connected to a daughter card via standard HSMC connectors. This standard SoC IOC will become the next generation of low-level IOC for the accelerator controls at Jefferson Lab.

Yan, Jianxun↗

DOE OSTI2014

Raexplore: Enabling Rapid, Automated Architecture Exploration for Full Applications

We present Raexplore, a performance modeling framework for architecture exploration. Raexplore enables rapid, automated, and systematic search of architecture design space by combining hardware counter-based performance characterization and analytical performance modeling. We demonstrate Raexplore for two recent manycore processors IBM Blue- Gene/Q compute chip and Intel Xeon Phi, targeting a set of scientific applications. Our framework is able to capture complex interactions between architectural components including instruction pipeline, cache, and memory, and to achieve a 3–22% error for same-architecture and cross-architecture performance predictions. Furthermore, we apply our framework to assess the two processors, and discover and evaluate a list of architectural scaling options for future processor designs.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

DOE OSTI2014

Load Balancing Scientific Applications

The largest supercomputers have millions of independent processors, and concurrency levels are rapidly increasing. For ideal efficiency, developers of the simulations that run on these machines must ensure that computational work is evenly balanced among processors. Assigning work evenly is challenging because many large modern parallel codes simulate behavior of physical systems that evolve over time, and their workloads change over time. Furthermore, the cost of imbalanced load increases with scale because most large-scale scientific simulations today use a Single Program Multiple Data (SPMD) parallel programming model, and an increasing number of processors will wait for the slowest one at the synchronization points. To address load imbalance, many large-scale parallel applications use dynamic load balance algorithms to redistribute work evenly. The research objective of this dissertation is to develop methods to decide when and how to load balance the application, and to balance it effectively and affordably. We measure and evaluate the computational load of the application, and develop strategies to decide when and how to correct the imbalance. Depending on the simulation, a fast, local load balance algorithm may be suitable, or a more sophisticated and expensive algorithm may be required. We developed a model for comparison of load balance algorithms for a specific state of the simulation that enables the selection of a balancing algorithm that will minimize overall runtime.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

A Pervasive Parallel Processing Framework for Data Visualization and Analysis at Extreme Scale

Most of today’s visualization libraries and applications are based off of what is known today as the visualization pipeline. In the visualization pipeline model, algorithms are encapsulated as “filtering” components with inputs and outputs. These components can be combined by connecting the outputs of one filter to the inputs of another filter. The visualization pipeline model is popular because it provides a convenient abstraction that allows users to combine algorithms in powerful ways. Unfortunately, the visualization pipeline cannot run effectively on exascale computers. Experts agree that the exascale machine will comprise processors that contain many cores. Furthermore, physical limitations will prevent data movement in and out of the chip (that is, between main memory and the processing cores) from keeping pace with improvements in overall compute performance. To use these processors to their fullest capability, it is essential to carefully consider memory access. This is where the visualization pipeline fails. Each filtering component in the visualization library is expected to take a data set in its entirety, perform some computation across all of the elements, and output the complete results. The process of iterating over all elements must be repeated in each filter, which is one of the worst possible ways to traverse memory when trying to maximize the number of executions per memory access. This project investigates a new type of visualization framework that exhibits a pervasive parallelism necessary to run on exascale machines. Our framework achieves this by defining algorithms in terms of functors, which are localized, stateless operations. Functors can be composited in much the same way as filters in the visualization pipeline. But, functors’ design allows them to be concurrently running on massive amounts of lightweight threads. Only with such fine-grained parallelism can we hope to fill the billions of threads we expect will be necessary for efficient computation on an exascale computer. This project concludes with a functional prototype containing pervasively parallel algorithms that perform demonstratively well on many-core processors. These algorithms are fundamental for performing data analysis and visualization at extreme scale.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Trinity Benchmarks on the Intel Xeon Phi (Knights Corner)

This report documents the early experiences with porting and performance analysis of the Tri-Lab Trinity benchmark applications on Intel Xeon Phi (Knights Corner) (KNC) processor. KNC, the second generation of the Intel Many Integrated Core (MIC) architectures, uses a large number of small P54C-x86 cores with wide vector units and is deployed as PCI bus attached process accelerators. Sandia has experimental test beds of small InifiniBand clusters and workstations to investigate the performance of the MIC architecture. On these experimental test beds the programming models that may be investigated are "offload", "symmetric" and "native". Among these program usage models our primary interest is in the so called "native" mode, because the planned Trinity system to be deployed in 2016 using the next generation MIC processor architecture called Knights Landing would be self-hosted. Trinity / NERSC-8 benchmark programs cover a variety of scientific disciplines and they were used to guide the procurement of these systems. Architectures such as the Intel MIC are well suited to study evolving processor architectures and a usage model commonly referred to as MPI + X that facilitates migration of our applications to use both coarse grain and fine grain parallelism. Our focus with the applications selected is on the efficacy of algorithms in these applications to take advantage of features like: large number of cores, wide vector units, higher-bandwidth and deeper memory sub-system. This is a first step towards understanding applications, algorithms and programming environments for Trinity and future exascale computing systems.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Model-Based Localizatiion in a Shallow Ocean Environment: A Sequential Bayesian/Optimization Approach

The shallow ocean is a dynamically changing medium leading to nonstationary statistical behavior when subjected to temperature, wind, surface variations, bottom interactions, noise and extraneous disturbances as well as other conditions that render it a uniquely challenging environment — especially from a signal processing perspective. Processors must account for and adapt to such instantaneous changes in order to be effective. Thus, a processor is required to “adapt” to these environmental variations while simultaneously providing meaningful estimates that are necessary for such applications as detection, localization, inversion and enhancement. In this paper, we develop a parametrically adaptive, sequential Bayesian processor capable of jointly estimating both modal functions and environmental parameters to provide enhanced estimates for a focused optimizer capable locating a target in the noisy shallow ocean environment.

42 ENGINEERING↗

DOE OSTI2020

Diagnosing and Destroying Non-Markovian Noise

Nearly every protocol used to analyze the performance of quantum information processors is based on an assumption that the errors experienced by the device during logical operations are constant in time and are insensitive to external contexts. This assumption is pervasive, rarely stated, and almost always wrong. Quantum devices that do behave this way are termed "Markovian:' but nearly every system we have ever probed has displayed drift or crosstalk or memory effects they are all non-Markovian. Strong non-Markovianity introduces spurious effects in characterization protocols and violates assumptions of the fault-tolerance threshold theorems. This SAND report details a three year laboratory-directed research and development (LDRD) project entitled, "Diagnosing and Destroying non-Markovian Noise in Quantum Information Processors." This program was initiated to build tools to study non-Markovian dynamics and quantum systems and develop robust methodologies for eliminating it. The program achieved a number of notable successes, including the first statistically rigorous protocol for identifying and characterizing drift in quantum systems, a formalism for modeling memory effects in quantum devices, and the successful suppression of drift in a Sandia trapped-ion quantum processor.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Parallel Time Integration for Constrained Optimization

The number of transistors in an average processor continues to increase, but individual clock speeds have plateaued. Those transistors are instead going into additional cores, increasing the number of different things that a processor can do at once and placing an emphasis on parallel computation. Many problems in scientific computing follow a time-evolution model, and it can be difficult to solve such problems in parallel across the temporal domain. The Multi-Grid Reduction In Time (MGRIT) algorithm, developed at Lawrence Livermore National Laboratory (LLNL), solves differential equations with a method designed specifically to take advantage of extreme numbers of processors by parallelizing across time. The Tri-diagonal MGRIT (TriMGRIT) algorithm, also developed at LLNL, is a generalization of MGRIT which enables parallel-in-time solving of a greater number of problems. Constrained optimization problems, in particular, may be solved in parallel using TriMGRIT. These consist of choosing a control function such that an objective functional is minimized, constrained by a differential-equation. We consider two such problems: applying torque to a pendulum to bring it to a gentle stop and moving a crowd of people from one distribution into another. We also perform some miscellaneous theoretical and practical research, including investigating the use of a line-search subroutine to refine intermediate TriMGRIT results and preliminary work on strategies for choosing operators for TriMGRIT to use.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

COLLABORATIVE DEVELOPMENT PROJECTS - PHOTONIC MEMORY CONTROLLER MODULE (P-MCM)

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high-performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM).

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2026

An Integrated Framework for Memory-Centric Analysis: From Trace Collection to Co-Design

The memory wall phenomenon—where advances in processor performance significantly outpace those in memory subsystems—poses a fundamental challenge for contemporary computing systems. In memory-bound applications, memory subsystem behavior dominates performance, yet existing analysis approaches present significant limitations: detailed microarchitectural simulators require days to weeks to simulate modest workloads; hardware performance counters provide only aggregate statistics that obscure temporal and spatial access patterns; and scaled simulation approaches face challenges in capturing certain behaviors that emerge at larger scales. These limitations reflect a processor-centric design philosophy increasingly misaligned with memory-bound workloads where detailed understanding of memory access patterns, cache hierarchy interactions, and contention is critical for effective optimization. This paper presents an integrated framework for memory-centric analysis that enables effective hardware-software co-design. We describe practical trace collection techniques, including hardware-assisted processor tracing with minimal overhead and portable software-based instrumentation with statistical sampling. We present multi-perspective analysis methods that examine memory behavior from temporal, sequential, spatial, and relational viewpoints, revealing distinct optimization opportunities invisible in aggregate metrics. We detail an architectural modeling framework that uses sampled traces with temporal interpolation and confidence-based filtering to evaluate cache and memory configurations. Evaluation on representative benchmarks demonstrates that this framework achieves practical accuracy (L2 cache errors of 2.64\%, confidence-filtered L3 errors of 9.92\%, bandwidth errors of 7.33\%) while providing substantial speedup (26.8×) over cycle-accurate simulation, enabling rapid design space exploration. We demonstrate how this integrated framework enables systematic identification of both hardware optimizations (memory controller tuning, bank partitioning, NUMA configuration) and software optimizations (data layout restructuring, prefetching strategies, memory-aware scheduling). Through this comprehensive treatment of the memory-centric analysis pipeline—from trace collection through architectural modeling to co-design application—we provide researchers and practitioners with practical techniques for addressing memory bottlenecks in contemporary computing systems.

Gajaria, Dhruv Mayur↗