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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,621 records · Page 90
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Design and Comparison of Cascaded H-Bridge, Modular Multilevel Converter, and 5-L Active Neutral Point Clamped Topologies for Motor Drive Applications

This paper presents the design procedure and comparison of converters currently used in medium-voltage high-power motor drive applications. For this purpose, the cascaded H-bridge (CHB), modular multilevel converter (MMC), and five-level active neutral point clamped (5-L ANPC) topologies are targeted. The design is performed using 1.7-kV insulated gate bipolar transistors (IGBTs) for CHB and MMC converters, and utilizing 3.3- and 4.5-kV IGBTs for 5-L ANPC topology as normally done in industry. The comparison is done between the designed converter topologies at three different voltage levels (4.16, 6.9, and 13.8 kV, with only the first two voltage levels in case of the 5-L ANPC) and two different power levels (3 and 5 MVA), in order to elucidate the dependence of different parameters on voltage and power rating. Finally, the comparison is done from several points of view such as efficiency, capacitive energy storage, semiconductor utilization, parts count (for measure of reliability), and power density.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

Switching Modes for Reduction of Peak Voltage Transients in GaN-Based Three Level ANPC Inverter

The switching pole voltage can transition between P,0, and N states in a three-level active neutral point clamped (ANPC) inverter. State transitions between 0-P and 0-N can be realized with different switching modes. Three switching modes- Short 1 , Short 2 , and Full are studied considering the effect of capacitive current paths. The role of clamping and inner switch on/off conditions is determined using simplified equivalent circuit models. Short 2 with clamping switch off is beneficial for turn-on overvoltage suppression but results in high turn-off overvoltage. Full mode with a parallel current sharing path is effective for turn-off overvoltage suppression but leads to high turn-on overvoltage. Hence, a Modified Full mode is proposed to achieve the simultaneous objective of overvoltage suppression at both turn-on and turn-off transient during high load currents. This benefits 3L ANPC operation at a low power factor with a high load current at fundamental voltage zero crossing points. Here, a 650V GaN-based three-level ANPC inverter prototype is designed and used to evaluate the switching modes and overvoltage suppression strategies through double pulse tests and continuous operation.

42 ENGINEERING↗
DOE OSTI2023

Capability of Impedance Measurement Using Spread Spectrum Time-Domain Reflectometry

Spread spectrum time-domain reflectometry (SSTDR) has been proposed for measuring electrical impedance on live, energized systems, in electrically noisy environments, or for measuring multiple channels simultaneously. Here we evaluate the capability of SSTDR for impedance measurement from near dc to 96 MHz and find that they agree very well with measurements from a vector network analyzer (VNA). Time gating is used to remove (calibrate out) transmission line effects. We evaluate the frequency ranges over which SSTDR at different modulation frequencies is accurate for the measurement of series resistive–capacitive ( RC ) loads and observe that fusing measurements from multiple modulation frequencies can broaden the effective measurement bandwidth.

14 SOLAR ENERGY↗
DOE OSTI2017

Novel Electrically Tunable Microwave Solenoid Inductor and Compact Phase Shifter Utilizing Permaloy and PZT Thin Films

A Permalloy (Py) thin film enabled tunable 3-D solenoid inductor is designed and fabricated. The special configuration of magnetic core is discussed and by selectively patterning Py thin film, the proposed tunable inductor can work at frequency up to several GHz range. The inductance of the solenoid inductor can be electrically tuned by dc current and the tunability is above 10%. Utilizing the implemented Py enabled tunable solenoid inductor and Lead Zirconate Titanate (PZT) thin film enabled metal-insulator-metal (MIM) capacitor, a compact fully electrically tunable lumped elements phase shifter is achieved. The tunable phase shifter has both inductive and capacitive tunability and the dual tunability significantly improves the tuning range and design flexibility. Moreover, the dual tunability is able to retain the equivalent characteristic impedance of the device in the process of the phase being tuned. Here, the phase of the device can be tuned by fully electrical methods and when dc current and dc voltage are provided, the length normalized phase tunability is up to 210°/cm

36 MATERIALS SCIENCE↗
DOE OSTI2019

Response of Waveguide-Integrated Germanium-on-Silicon p-i-n Photodiodes to Neutron Displacement Damage

The effects of 14-MeV neutron displacement damage (DD) on waveguide-integrated germanium-on-silicon p-i-n photodiodes (PDs) for silicon photonics have been investigated up to fluences of 7.5×1012 n/cm2 (14 MeV), or 1.4×1013 n1-MeVeq/cm2(Si). The study includes measurements of dark current-voltage characteristics across temperature from 150-375 K, measurements of PD junction capacitance, spectral response measurements from 1260 nm to 1360 nm, and frequency response measurements. The devices are found to be susceptible to DD-induced carrier removal effects; however, they also continue to operate without meaningful impact to performance for the DD dose levels examined. Since the PD test chips include silicon photonic integrated grating couplers and waveguides which carry the optical signal to the PD, some assessment of the impact of DD on these passive devices can also be inferred. Finally, this work does not examine the short-term annealing or transient behavior of the DD, and instead has only considered the lasting damage that remains after any initial period of room temperature annealing.

42 ENGINEERING↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2025

Improving Longitudinal Impedance of Inductive Inserts

In this article, we discuss methods for improving the longitudinal impedance of inductive inserts used for space charge compensation in the proton storage ring (PSR) at Los Alamos Neutron Science Center (LANSCE) Facility. The PSR relies on inductive inserts to counteract the capacitive impedance produced by the space charge of the proton beam, which can otherwise lead to beam debunching. Existing inductive inserts, which utilize Toshiba M4C21A ferrite, have been effective but require heating to reduce resistive components that can cause instabilities at higher frequencies. This article explores the potential of alternative ferrite materials, specifically National Magnetics C2050, to enhance the performance of these inserts by reducing the need for heating and minimizing resistive impedance. Through both analytical modeling and CST Particle Studio simulations, it is demonstrated that optimized ferrite materials and geometries can significantly improve space charge compensation while mitigating instability risks, ultimately enhancing the performance of the PSR.

43 PARTICLE ACCELERATORS↗
DOE OSTI2026

Readout Noise of Digital Frequency Multiplexed TES Detectors for CUPID

The superconducting transition-edge sensor (TES) detectors have been the standard in cosmic microwave background (CMB) experiments for almost two decades and are now being adapted for use in nuclear physics, such as neutrinoless double beta decay searches. In this article, we focus on a new high-bandwidth frequency multiplexed TES readout system developed for CUPID, a neutrinoless double beta decay experiment that will replace CUORE. In order to achieve the high energy resolution requirements for CUPID, the readout noise of the system must be kept to a minimum. Low TES operating resistance and long wiring between the readout SQUID and the warm electronics are needed for CUPID, prompting a careful consideration of the design parameters of this application of frequency multiplexing. In this work, we characterize the readout noise of the newly designed frequency multiplexed TES readout system for CUPID and construct a noise model to understand it. Here, we find that current sharing between the SQUID coil impedance and other branches of the circuit, as well as the long output wiring, worsen the readout noise of the system. To meet noise requirements, a SQUID with a low input inductance, high transimpedance, and/or low dynamic impedance is needed, and the wiring capacitance should be kept as small as possible. Alternatively, the option of adding a cryogenic low-noise amplifier at the output of the SQUID should be explored.

CUPID↗
DOE OSTI2017

Temperature-Dependent Characterization, Modeling, and Switching Speed-Limitation Analysis of Third-Generation 10-kV SiC MOSFET

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. Here, a double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simple behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.

10-kV silicon carbide (SiC) metal–oxide–semiconduc↗
DOE OSTI2020

Capacitor Voltage Ripple Estimation and Optimal Sizing of Modular Multi-Level Converters for Variable-Speed Drives

This article deals with the sizing of submodule capacitors for modular multilevel converters (MMCs) used for variable speed drives for medium voltage and high voltage electric machines. Variable speed drives are required to run over a wide frequency range from zero to a few hundred Hz or even over 1 kHz. Under low frequency operation (<30 Hz), a large current ripple flowing through the MMC submodule capacitors will cause significant capacitor voltage fluctuation. This article proposes an optimal submodule capacitor selection method based on the common-mode voltage injection. The proposed sizing model includes two functions: 1) accurately estimating the capacitor voltage ripple based on the drive system parameters; and 2) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and experimental results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.

42 ENGINEERING↗
DOE OSTI2020

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. Furthermore, these results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

42 ENGINEERING↗
DOE OSTI2020

Modular Multilevel Converter (MMC) Modeling Considering Submodule Voltage Sensor Noise

The modular multilevel converter (MMC) is a popular topology in medium- and high-voltage applications, and many efforts have been spent on MMC modeling. However, the impact of submodule voltage sensor noise (SVSN), which becomes more severe due to increasing switching speed of power semiconductors and compact submodule design, has not been considered in conventional models. In this letter, the SVSN is introduced by coupling capacitances between the sensor and power stage in an MMC switching model. Furthermore, the SVSN impact is considered in an MMC average model based on derivation of the relationship between the SVSN and the duty cycle. Here, the proposed MMC switching model and average model considering the SVSN are validated by comparing simulations with experimental results in an MMC prototype using 10-kV SiC MOSFETS.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Factors and Considerations for Modeling Loss of a GaN-based Inverter

The article investigates the impacts of four often-neglected factors on the loss model of a GaN-based full-bridge inverter: parasitic capacitance of the devices, dynamics of junction temperature (Tj) under time-varying power dissipation (Ploss), case temperature estimation, and detailed considerations of the passive components. Procedures to calculate the converter loss considering the above factors are proposed and implemented. A 4.5-kW hard-switching inverter prototype using gallium nitrite (GaN) high-electron-mobility transistors is used to experimentally demonstrate the impact of each factor on the converter loss model. Furthermore, it is found that the accuracy of a converter loss model is mainly affected by the passive components at the light load condition, whereas the thermal and loss models of the active components become the major factors as the output power increases. The results show that after considering the above factors, the converter loss discrepancy between calculation and measurement can be reduced from 30.6 W (28%) to 2.5 W (less than 3%) at heavy load (Po = 4.5 kW), while at the light load condition (Po = 500 W), it is reduced from 3.9 W (28%) to 2.6 W (16%). Furthermore, the difference between simulated and measured case temperature of the GaN devices is within 6 °C.

42 ENGINEERING↗
DOE OSTI2021

Planar Transformer With Asymmetric Integrated Leakage Inductance Using Horizontal Air Gap

This article presents a novel planar-based transformer winding and core structure with controllable leakage inductance generation for integrated magnetics applications. As a result of limitations in integrated magnetics from the literature, a new approach is proposed utilizing semi-interleaved windings and controllable leakage via a leakage flux core leg featuring a horizontal air gap. Here, the proposed transformer design is analyzed via detailed reluctance modeling to determine closed-form equations for the magnetizing and asymmetrically distributed leakage inductances. Next, a genetic-algorithm-based multiobjective design optimization problem is developed, seeking to minimize the core and winding losses of the proposed transformer subject to a set of parametric and geometric constraints in a dc-ac dual-active-bridge topology for microinverter applications. The optimization was extended to include other integrated magnetic structures from the literature, where it is determined that the proposed transformer is superior from the perspectives of efficiency, footprint area, and parasitic capacitance. Based on the results of the optimization analysis, two designs with theoretical transformer California Energy Commission (CEC) efficiency drops (i.e., CEC efficiency reduction specifically due to the transformer loss mechanisms) of 1.19% and 0.83% were fabricated and evaluated for electrical and thermal performance in the proposed 40 V, 400 W microinverter.

42 ENGINEERING↗
DOE OSTI2022

Predictive Direct DC-Link Control for 7.2 kV Three-Port Low-Inertia Solid-State Transformer With Active Power Decoupling

Promising for applications including renewable energy and electric vehicle fast charging, a medium-voltage (MV) solid-state transformer (SST) typically has multiple modules series stacked, which requires the modules to be single phase. One critical issue of the single-phase SST is the double-line-frequency power ripple. Traditionally, large passives are used to buffer the ripple, resulting in significantly increased volume and cost. This article for the first time proposes active power decoupling (APD) for the SST and a predictive direct DC-link control method, using a current-source single-stage SST as an example. An electrolytic capacitor-less buffer port is used to absorb the ripple, which tolerates up to a 30% voltage ripple for small capacitance. The APD SST control is challenging. First, the current-source SST realizes isolation, DC link, and multiport in a single stage. Second, different from conventional SSTs or APD converters, the low-inertia DC link in this SST has a 40% switching ripple, which is difficult to stabilize. To address the control challenge, a direct DC-link control architecture and a predictive control method are proposed. Simulation and experimental results verify the proposed control method on an MV SiC modular soft-switching solid-state transformer (M-S4T) prototype. Here, the proposed APD reduces the SST volume by 53.8%. Importantly, the proposed concept is not limited to the M-S4T but is generic to other SSTs or APD converters.

14 SOLAR ENERGY↗
DOE OSTI2022

1 kV, 10-kW SiC-Based Quadruple Active Bridge DCX Stage in a DC to Three-Phase AC Module for Medium-Voltage Grid Integration

Interfacing low voltage dc to medium voltage three-phase ac grid is often based on series-stackable modular converter architectures. To minimize energy storage requirements, it is advantageous to employ a quadruple active bridge (QAB) stage operating as a "dc transformer" in each stackable module. The QAB stage offers three isolated dc link voltages, which then allow for flexible stacking of three single-phase dc-to-ac inverter stages. Each of the module phases processes a pulsating power having a component at twice the line frequency. This presents a challenge in maintaining zero voltage switching (ZVS) on the secondary sides of the QAB during low-power portions of the line cycle. This article is focused on the design of the QAB stage. A detailed analysis of ZVS switching waveforms is presented, including effects of nonlinear device capacitances. It is shown how ZVS can be achieved at all times using a relatively small circulating current provided by the magnetizing inductance of the high-frequency transformer. Analytical expressions are given for the optimal values of the magnetizing inductance and the dead times of the QAB primary and secondary bridges. This approach is verified by experimental results on a 1 kV, 10-kW SiC-based prototype, demonstrating a relatively flat efficiency curve with a peak efficiency of 97.1% at 75% load.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

Stability Considerations for Virtual Capacitor Control in Constant Power DC Loads

In a DC grid, constant power loads (CPLs) necessitate a large bus capacitor to prevent negative impedance instability. Some of the capacitance can be realized virtually through CPL control to reduce the bus capacitor size. Here, this paper analytically studies system stability with virtual capacitor control. We demonstrate that the effectiveness of virtual capacitor control is highly sensitive to the implementation of the derivative action required to emulate the capacitor. For the first time, we theoretically demonstrate that a virtual capacitor can stabilize the system without any physical bus capacitor, provided that a set of analytically derived conditions are met. However, this stabilization is not achievable in practice due to the influence of non-idealities. In an example system requiring a $14$ mF capacitor to stably support the CPL, we show that stability can be achieved through virtual capacitor control, using only a 2 mF physical capacitor to account for the switching ripple non-idealities. Hardware-in-the-loop tests verify the analysis.

24 POWER TRANSMISSION AND DISTRIBUTION↗