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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Using rheo-electric measurements, we revealed a power-law scaling that quantitatively describes the shear rheology of lithium-ion battery slurry, and identified shear-induced structure memory through the carbon-phase electrical conductivity.
We have entered the Noisy Intermediate-Scale Quantum Era. A plethora of quantum processor prototypes allow evaluation of potential of the Quantum Computing paradigm in applications to pressing computational problems of the future. Growing data input rates and detector resolution foreseen in High-Energy LHC (2030s) experiments expose the often high time and/or space complexity of classical algorithms. Quantum algorithms can potentially become the lower-complexity alternatives in such cases. In this work we discuss the potential of Quantum Associative Memory (QuAM) in the context of LHC data triggering. We examine the practical limits of storage capacity, as well as store and recall errorless efficiency, from the viewpoints of the state-of-the-art IBM quantum processors and LHC real-time charged track pattern recognition requirements. We present a software prototype implementation of the QuAM protocols and analyze the topological limitations for porting the simplest QuAM instances to the public IBM 5Q and 14Q cloud-based superconducting chips.
Effects of GaSb doping on phase change characteristics of Ge-Sb-Te material are investigated by in situ resistance and x-ray diffraction measurement, optical spectroscopy, and x-ray photoelectron spectroscopy. The crystallization temperature and data retention of Ge-Sb-Te material increase significantly by the addition of GaSb, which results from the high thermal stability of amorphous GaSb. In addition, GaSb-doped Ge-Sb-Te material exhibits faster crystallization speed due to the change in electronic states as a result of the formation of chemical bonds with Ga element. Incorporation of GaSb is highly effective way to enhance the comprehensive performance of Ge-Sb-Te material for phase change memory.
We show that the energy dissipated to write bits in spin-transfer-torque random access memory can be reduced by an order of magnitude if a surface acoustic wave (SAW) is launched underneath the magneto-tunneling junctions (MTJs) storing the bits. The SAW-generated strain rotates the magnetization of every MTJs' soft magnet from the easy towards the hard axis, whereupon passage of a small spin-polarized current through a target MTJ selectively switches it to the desired state with > 99.99% probability at room temperature, thereby writing the bit. The other MTJs return to their original states at the completion of the SAW cycle.
In this paper, multi-layer Zn:SiO{sub 2}/SiO{sub 2} structure is introduced to reduce the operation power consumption of resistive random access memory (RRAM) device by modifying the filament formation process. And the configuration of multi-layer Zn:SiO{sub 2}/SiO{sub 2} structure is confirmed and demonstrated by auger electron spectrum. Material analysis together with conduction current fitting is applied to qualitatively evaluate the carrier conduction mechanism on both low resistance state and high resistance state. Finally, single layer and multilayer conduction models are proposed, respectively, to clarify the corresponding conduction characteristics of two types of RRAM devices.
Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.
We propose a write scheme for perpendicular spin-transfer torque magnetoresistive random-access memory that significantly reduces the required tunnel current density and write energy. A sub-nanosecond in-plane polarized spin current pulse is generated using the spin-Hall effect, disturbing the stable magnetic state. Subsequent switching using out-of-plane polarized spin current becomes highly efficient. Through evaluation of the Landau-Lifshitz-Gilbert equation, we quantitatively assess the viability of this write scheme for a wide range of system parameters. A typical example shows an eight-fold reduction in tunnel current density, corresponding to a fifty-fold reduction in write energy, while maintaining a 1 ns write time.
High current density is indispensable to shift domain walls (DWs) in magnetic nanowires, which limits the using of racetrack memory (RM) for low power and high density purposes. In this paper, we present perpendicular-magnetic-anisotropy (PMA) Co/Ni RM with global magnetic field assistance, which lowers the current density for DW motion. By using a compact model of PMA RM and 40 nm design kit, we perform mixed simulation to validate the functionality of this structure and analyze its density potential. Stochastic DW motion behavior has been taken into account and statistical Monte-Carlo simulations are carried out to evaluate its reliability performance.
We report a rare consequence of memory effect in dielectric response (ϵ) and magnetic field induced rejuvenation in a relaxor-type multiferroic chalcogenide, CuCrS{sub 2}. Despite reasonably high conductivity, we are able to detect significant spontaneous polarization using an improvised technique verifying ferroelectric (FE) order. Concomitant appearance of both FE and antiferromagnetic orders authenticates multiferroicity. A smeared out FE transition and strong frequency dependence of the broadened peak in ϵ obeying Dynamical scaling law signify relaxor properties. We discuss the role of geometrical frustration in the antiferromagnetically coupled layered triangular lattice and metal ligand hybridization for these unusual properties.
Fast read-out of two to six charges per dot from the ground and first excited state in a quantum dot (QD)-based memory is demonstrated using a two-dimensional electron gas. Single-shot measurements on modulation-doped field-effect transistor structures with embedded InAs/GaAs QDs show read-out times as short as 3 ns. At low temperature (T = 4.2 K) this read-out time is still limited by the parasitics of the setup and the device structure. Faster read-out times and a larger read-out signal are expected for an improved setup and device structure.
The nanoscale crystal nuclei in an amorphous Ge{sub 2}Sb{sub 2}Te{sub 5} bit in a phase change memory device were evaluated by fluctuation transmission electron microscopy. The quench time in the device (∼10 ns) afforded more and larger nuclei in the melt-quenched state than in the as-deposited state. However, nuclei were even more numerous and larger in a test structure with a longer quench time (∼100 ns), verifying the prediction of nucleation theory that slower cooling produces more nuclei. It also demonstrates that the thermal design of devices will strongly influence the population of nuclei, and thus the speed and data retention characteristics.
Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (J{sub g}) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO{sub 2}/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electrically active defects and is essential to achieve a low leakage current in the MIM capacitor.
Metal-oxide-semiconductor capacitors made of the nanocrystalline cadmium selenide nc-CdSe embedded Zr-doped HfO{sub 2} high-k stack on the p-type silicon wafer have been fabricated and studied for their charge trapping, detrapping, and retention characteristics. Both holes and electrons can be trapped to the nanocrystal-embedded dielectric stack depending on the polarity of the applied gate voltage. With the same magnitude of applied gate voltage, the sample can trap more holes than electrons. A small amount of holes are loosely trapped at the nc-CdSe/high-k interface and the remaining holes are strongly trapped to the bulk nanocrystalline CdSe site. Charges trapped to the nanocrystals caused the Coulomb blockade effect in the leakage current vs. voltage curve, which is not observed in the control sample. The addition of the nanocrystals to the dielectric film changed the defect density and the physical thickness, which are reflected on the leakage current and the breakdown voltage. More than half of the originally trapped holes can be retained in the embedded nanocrystals for more than 10 yr. The nanocrystalline CdSe embedded high-k stack is a useful gate dielectric for this nonvolatile memory device.
We studied how electrical erasing of indium gallium zinc oxide-thin-film-transistor memory was improved by adding concurrent irradiation with monochromatic light (ML). At fixed gate bias, irradiating at wavelengths of ≤500 nm increased the erasing window (ΔV{sub th-e}) significantly: At a gate bias of −20 V and an erasing time of 5 min, ML irradiation at 400 nm increased ΔV{sub th-e} from 0.29 to 3.21 V. ΔV{sub th-e} increased incrementally with gate bias, erasing time, and ML power density, particularly at short ML wavelengths. Analyzing our experimental results, we discuss the underlying erasure mechanisms.
The effects of fluorine treatment on the charge-trapping characteristics of thin ZrO{sub 2} film are investigated by physical and electrical characterization techniques. The formation of silicate interlayer at the ZrO{sub 2}/SiO{sub 2} interface is effectively suppressed by fluorine passivation. However, excessive fluorine diffusion into the Si substrate deteriorates the quality of the SiO{sub 2}/Si interface. Compared with the ZrO{sub 2}-based memory devices with no or excessive fluorine treatment, the one with suitable fluorine-treatment time shows higher operating speed and better retention due to less resistance of built-in electric field (formed by trapped electrons) against electron injection from the substrate and smaller trap-assisted tunneling leakage, resulting from improved ZrO{sub 2}/SiO{sub 2} and SiO{sub 2}/Si interfaces.
N doping is proposed to enlarge sensing margin of W{sub 0.08}(Sb{sub 2}Te){sub 0.92} based high-temperature phase-change memories (PCMs). The sensing margin is increased from 30 to 5 × 10{sup 3}, with an increase from 145 °C to 158 °C in data retention. The grain size is reduced to 10 nm. The PCM based on N-W{sub 0.08}(Sb{sub 2}Te){sub 0.92} shows the fast operation speed of 30 ns and good cycling ability of >10{sup 3}. By X-ray photoelectron spectroscopy and ab initio calculation, the W atoms are suggested to locate in the Sb positions and interstices of the lattice. The W atoms in interstice will bond to N atoms during N doping.
We demonstrate an electrolyte-based voltage tunable vanadium dioxide (VO{sub 2}) memory metasurface. Large spatial scale, low voltage, non-volatile switching of terahertz (THz) metasurface resonances is achieved through voltage application using an ionic gel to drive the insulator-to-metal transition in an underlying VO{sub 2} layer. Positive and negative voltage application can selectively tune the metasurface resonance into the “off” or “on” state by pushing the VO{sub 2} into a more conductive or insulating regime respectively. Compared to graphene based control devices, the relatively long saturation time of resonance modification in VO{sub 2} based devices suggests that this voltage-induced switching originates primarily from electrochemical effects related to oxygen migration across the electrolyte–VO{sub 2} interface.
The time-resolved reflectivity measurements were carried out on the interfacial phase change memory (iPCM) materials ([(GeTe){sub 2}(Sb{sub 2}Te{sub 3}){sub 4}]{sub 8} and [(GeTe){sub 2}(Sb{sub 2}Te{sub 3}){sub 1}]{sub 20}) as well as conventional Ge{sub 2}Sb{sub 2}Te{sub 5} alloy at room temperature and above the RESET-SET phase transition temperature. In the high-temperature phase, coherent phonons were clearly observed in the iPCM samples while drastic attenuation of coherent phonons was induced in the alloy. This difference strongly suggests the atomic rearrangement during the phase transition in iPCMs is much smaller than that in the alloy. These results are consistent with the unique phase transition model in which a quasi-one-dimensional displacement of Ge atoms occurs for iPCMs and a conventional amorphous-crystalline phase transition takes place for the alloy.