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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,675 records · Page 93
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

Comparison of Analytical Predictions and Experimental Results for a Dual Brayton Power System

NASA Glenn Research Center (GRC) contracted Barber- Nichols, Arvada, CO to construct a dual Brayton power conversion system for use as a hardware proof of concept and to validate results from a computational code known as the Closed Cycle System Simulation (CCSS). Initial checkout tests were performed at Barber- Nichols to ready the system for delivery to GRC. This presentation describes the system hardware components and lists the types of checkout tests performed along with a couple issues encountered while conducting the tests. A description of the CCSS model is also presented. The checkout tests did not focus on generating data, therefore, no test data or model analyses are presented.

Johnson, Paul↗
NASA NTRS2007

Comparison of Analytical Predictions and Experimental Results for a Dual Brayton Power System (Discussion on Test Hardware and Computer Model for a Dual Brayton System)

NASA Glenn Research Center (GRC) contracted Barber-Nichols, Arvada, CO to construct a dual Brayton power conversion system for use as a hardware proof of concept and to validate results from a computational code known as the Closed Cycle System Simulation (CCSS). Initial checkout tests were performed at Barber- Nichols to ready the system for delivery to GRC. This presentation describes the system hardware components and lists the types of checkout tests performed along with a couple issues encountered while conducting the tests. A description of the CCSS model is also presented. The checkout tests did not focus on generating data, therefore, no test data or model analyses are presented.

Johnson, Paul K.↗
DOE OSTI2021

Achieving performance portability in Gaussian basis set density functional theory on accelerator based architectures in NWChemEx

The numerical integration of the exchange–correlation (XC) potential is one of the primary computational bottlenecks in Gaussian basis set Kohn–Sham density functional theory (KS-DFT). To achieve optimal performance and accuracy, care must be taken in this numerical integration to preserve local sparsity as to allow for near linear weak scaling with system size. This leads to an integration scheme with several performance critical kernels which must be hand optimized for each architecture of interest. As the set of available accelerator hardware goes more diverse, a key challenge for developers of KS-DFT software is to maintain performance portability across a wide range of computational architectures. In this article, we examine a modular software design pattern which decouples the implementation details of performance critical kernels from the expression of high-level algorithmic workflows in a device-agnostic language such as C++; thus allowing for developers to target existing and emerging accelerator hardware within a single code base. We consider the efficacy of such a design pattern in the numerical integration of the XC potential by demonstrating its ability to achieve performance portability across a set of accelerator architectures which are representative of those on current and future U.S. Department of Energy Leadership Computing Facilities.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1998

Development of Lead Free Energy Absorber for Space Shuttle Blast Container

The Space Shuttle vehicle (SSV) is connected to the mobile launch platform (MLP) by four aft skirt hold down studs on each solid rocket booster (SRB). Prior to lift-off, the frangible nuts inside the aft skirt blast containers (BC) are severed into two nut halves by two pyrotechnic booster cartridges. This action releases the SSV and allows the hold down studs to eject through the aft skirt bore and then down into the MLP. USBI has been tasked to upgrade the BC for two specific reasons; 1. to eliminate lead for environmental concerns, and 2. to reduce the chance of nut recontact with the holddown stud. Nut recontact with the stud has been identified as a likely contributor to stud hangups. This upgrade will replace the lead liner with an aluminum foam material. The aluminum foam used as a energy absorber is a proven design in many other aerospace/defense applications. Additional benefits of using the open cell, energy absorbent aluminum foam in place of the solid lead liner are: A. Lead handling/ exposure, and possible contamination, along with hazardous waste disposal will be eliminated; B. Approximately 200 lbs. weight savings will be contributed to each Space Shuttle flight by using aluminum foam over lead; C. The new aluminum liner is designed to catch all shrapnel from frangible nuts thus virtually eliminating chance of foreign object debris (FOD) exiting the HDP, and causing potential damage to the vehicle; D. Potential of using the lighter aluminum liner over lead, allows for easier assembly and disassembly of blast container elements, also allowing for improvements in safety, operator handling, and efficiency of operations. Six BC firing tests will be required to determine if the new liner material will perform in a way to decrease the chance of stud hangups and enhance the ability of the BC to retain blast debris. Testing will be performed at the Kennedy Space Center (KSC) facility known as the Launch Equipment Test Facility (LETF), and will simulate the SRB hold- down post, with actual BC hardware and pyrotechnics assembled, and then test fired. Initial testing was performed in 1997 using a frangible nut in a static drop test over lead and aluminum foam sheet materials. The aluminum foam showed a dramatic improvement of energy absorption over the lead liner material. Proof-of-Principle testing at the KSC-LETF commenced in May, 1998, and is expected to be completed by June, 1998.

Ingram, T.↗
NASA NTRS1991

A hardware-oriented algorithm for floating-point function generation

An algorithm is presented for performing accurate, high-speed, floating-point function generation for univariate functions defined at arbitrary breakpoints. Rapid identification of the breakpoint interval, which includes the input argument, is shown to be the key operation in the algorithm. A hardware implementation which makes extensive use of read/write memories is used to illustrate the algorithm.

O'Grady, E. Pearse↗
NASA NTRS2001

Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of radiation tolerant RAM-based field programmable gate array (FPGA) technology to develop a reconfigurable processor that combines the flexibility of a general purpose processor running software with the performance of application specific processing hardware for a variety of high performance computing applications.

Darrin, Ann Garrison↗
NASA NTRS2005

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Ferguson, Roscoe C.↗
NASA NTRS2019

Combined Qualification Vibration Testing and Fixed Base Modal Testing Utilizing a Fixed Based Correction Method

Vibration testing spaceflight hardware is a vital, but time consuming and expensive endeavor. Traditionally modal tests are performed at the component, subassembly, or system level, preferably free-free with mass loaded interfaces or fixed base on a seismic mass to identify the fundamental structural dynamic (modal) characteristics. Vibration tests are then traditionally performed on single-axis slip tables at qualification levels that envelope the maximum predicted flight environment plus 3 dB and workmanship in order to verify the spaceflight hardware can survive its flight environment. These two tests currently require two significantly different test setups, facilities, and ultimately reconfiguration of the spaceflight hardware. The vision of this research is to show how traditional fixed-base modal testing can be accomplished using vibration qualification testing facilities, which not only streamlines testing and reduces test costs, but also opens up the possibility of performing modal testing to untraditionally high excitation levels that provide for test-correlated finite element models to be more representative of the spaceflight hardware's response in a flight environment. This paper documents the first steps towards this vision, which is the comparison of modal parameters identified from a traditional fixed-based modal test performed on a modal floor and those obtained by utilizing a fixed based correction method with a large single-axis electrodynamic shaker driving a slip table supplemented with additional small portable shakers driving on the slip table and test article. To show robustness of this approach, the test article chosen is a simple linear weldment, whose mass, size, and modal parameters couple well with the dynamics of the shaker/slip table. This paper will show that all dynamics due to the shaker/slip table were successfully removed resulting in true fixed-base modal parameters, including modal damping, being successfully extracted from a traditional style base-shake vibration test setup.

Winkel, James P.↗
DOE OSTI2020

A Benthic Habitat Monitoring Approach for Marine and Hydrokinetic Sites (Final Technical Report)

This final technical report summarizes the work completed as part of the Standardized and Cost-Effective Benthic Habitat Mapping and Monitoring Tools for MHK Environmental Assessments project funded by U.S. Department of Energy (DOE) under contract DE-EE007826 to Integral Consulting Inc. The overall goal of this project was to demonstrate a consistent, repeatable, and semi-automated seafloor and sediment mapping approach for rapidly characterizing benthic physical and biological/habitat conditions to support marine environmental assessments for marine and hydrokinetic energy sites. The approach evaluated combines sediment profile imaging and plan view (SPI/PV) technology with multibeam echosounder surveys as an effective and low-cost benthic habitat mapping protocol. A key innovation was the development of a semi-automated computer vision system that standardizes the extraction of data from the SPI/PV images. Other elements of the project were SPI camera hardware modifications, including the design and fabrication of a prototype “power” SPI camera to improve camera prism penetration in firm substrates, and outreach to agency regulators and other stakeholders on this habitat mapping approach. This technical report consists of five main subsections that summarize: 1) the benthic mapping approach; 2) benthic mapping results from the three areas’ surveys; 3) the development and performance of the image processing algorithms; 4) SPI camera hardware improvements and prototype testing; and 5) the regulatory outreach efforts.

16 TIDAL AND WAVE POWER↗
NASA NTRSDate not supplied

DC Performance Testing of MgB2 Superconducting Straight Wire Samples

To enable turboelectric aircraft that utilize fully superconducting motors and generators, testing of high-current, low-AC-loss superconducting wires and coils must be performed. A preliminary investigation was conducted on the critical current capabilityof a magnesium diboride sample and on the complications that arise from testing the sample with a cryocooler. While a cryocooler provides the benefit of a wide and continuous operating temperature range, cooling a sample by conduction through solid media without a heat-exchange gas is difficult. This paper outlines the hardware and software used to conduct the first DC performance tests on magnesium diboride superconducting samples, along with several check-out tests and mitigation steps needed to produce quality superconducting data using a cryocooler rather than a cryogen

Superconductor↗
NASA NTRS1996

Age Life Evaluation of Space Shuttle Crew Escape System Pyrotechnic Components Loaded with Hexanitrostilbene (HNS)

Determining deterioration characteristics of the Space Shuttle crew escape system pyrotechnic components loaded with hexanitrostilbene would enable us to establish a hardware life-limit for these items, so we could better plan our equipment use and, possibly, extend the useful life of the hardware. We subjected components to accelerated-age environments to determine degradation characteristics and established a hardware life-limit based upon observed and calculated trends. We extracted samples using manufacturing lots currently installed in the Space Shuttle crew escape system and from other NASA programs. Hardware included in the study consisted of various forms and ages of mild detonating fuse, linear shaped charge, and flexible confined detonating cord. The hardware types were segregated into 5 groups. One was subjected to detonation velocity testing for a baseline. Two were first subjected to prolonged 155 F heat exposure, and the other two were first subjected to 255 F, before undergoing detonation velocity testing and/or chromatography analysis. Test results showed no measurable changes in performance to allow a prediction of an end of life given the storage and elevated temperature environments the hardware experiences. Given the lack of a definitive performance trend, coupled with previous tests on post-flight Space Shuttle hardware showing no significant changes in chemical purity or detonation velocity, we recommend a safe increase in the useful life of the hardware to 20 years, from the current maximum limits of 10 and 15 years, depending on the hardware.

Hoffman, William C., III↗
NASA NTRS1980

Demonstration Advanced Avionics System (DAAS) functional description

A comprehensive set of general aviation avionics were defined for integration into an advanced hardware mechanization for demonstration in a Cessna 402B aircraft. Block diagrams are shown and system and computer architecture as well as significant hardware elements are described. The multifunction integrated data control center and electronic horizontal situation indicator are discussed. The functions that the DAAS will perform are examined. This function definition is the basis for the DAAS hardware and software design.

Source record↗
NASA NTRS2019

Computational Performance of Progressive Damage Analysis of Composite Laminates using Abaqus/Explicit with 16 to 512 CPU Cores

The computational scaling performance of progressive damage analysis using Abaqus/ Explicit is evaluated and quantified using from 16 to 512 CPU cores. Several analyses were conducted on varying numbers of cores to determine the scalability of the code on five NASA high performance computing systems. Two finite element models representative of typical models used for progressive damage analysis of composite laminates were used. The results indicate a 10 to 15 times speed up scaling from 24 to 512 cores. The run times were modestly reduced with newer generations of CPU hardware. If the number of degrees of freedom is held constant with respect to the number of cores, the model size can be increased by a factor of 20, scaling from 16 to 512 cores, with the same run time. An empirical expression was derived relating run time, the number of cores, and the number of degrees of freedom. Analysis cost was examined in terms of software tokens and hardware utilization. Using additional cores reduces token usage since the computational performance increases more rapidly than the token requirement with increasing number of cores. The in- crease in hardware cost with increasing cores was found to be modest. Overall the results show relatively good scalability of the Abaqus/Explicit code on up to 512 cores.

Bergan, A. C.↗
DOE OSTI2020

Logic in Memory Emulator

Logic in Memory Emulator (LiME) is a hardware/software tool specially designed for memory system evaluation and experiment. Emerging memories display a wide range of bandwidths, latencies, and capacities, making it challenging for the computer architect to navigate the design space of potential memory configurations, and for the application developer to assess performance implications of using such memories. With the LiME framework, architectural ideas can be prototyped in great detail yet with sufficient performance to support realistic evaluation on long running applications. LiME consists of two fundamental components: 1) the hardware and OS infrastructure for the emulator, and 2) a suite of benchmark applications to assist in characterizing the performance of current and future computer architectures. Some of the applications have been collected from other open source projects. Uses: Logging, replay and analysis of an application's memory behavior Evaluate impact of emerging memory technology on application performance. Emulate complex memory interactions in whole applications orders of magnitude faster than software simulation. Emulate acceleration hardware co-located with the memory subsystem. Features: Capture and log external memory accesses to a separate off-chip memory device without affecting application execution. Memory traces include the address, length, timestamp, and optionally the data for each transaction. Captured trace data can be saved to an SD card for off-line analysis. Configure a wide range of memory latencies in sub-nanosecond increments that encompass highbandwidth and storage class memories. Specify regions of interest (ROI) in applications to reduce the amount of trace data captured for analysis. Currently supports execution on Xilinx Zynq SoC which integrates an ARM processor with FPGA logic on a single device. Applications can be run under Linux or in bare metal mode on the ARM cores.

Jain, AbhishekK↗
DOE OSTI2019

RDMA vs. RPC for Implementing Distributed Data Structures

Distributed data structures are key to implementing scalable applications for scientific simulations and data analysis. In this paper we look at two implementation styles for distributed data structures: remote direct memory access (RDMA) and remote procedure call (RPC). We focus on operations that require individual accesses to remote portions of a distributed data structure, e.g., accessing a hash table bucket or distributed queue, rather than global operations in which all processors collectively exchange information. We look at the trade-offs between the two styles through microbenchmarks and a performance model that approximates the cost of each. The RDMA operations have direct hardware support in the network and therefore lower latency and overhead, while the RPC operations are more expressive but higher cost and can suffer from lack of attentiveness from the remote side. We also run experiments to compare the real-world performance of RDMA- and RPC-based data structure operations with the predicted performance to evaluate the accuracy of our model, and show that while the model does not always precisely predict running time, it allows us to choose the best implementation in the examples shown. We believe this analysis will assist developers in designing data structures that will perform well on current network architectures, as well as network architects in providing better support for this class of distributed data structures.

distributed data structures↗
NASA NTRS2014

Extravehicular Activity (EVA) Hardware & Operations Overview

The objectives of this presentation are to: Define Extravehicular Activity (EVA), identify the reasons for conducting an EVA, and review the role that EVA has played in the space program; Identify the types of EVAs that may be performed; Describe some of the U.S. Space Station equipment and tools that are used during an EVA, such as the Extravehicular Mobility Unit (EMU), the Simplified Aid For EVA Rescue (SAFER), the International Space Station (ISS) Joint Airlock and Russian Docking Compartment 1 (DC-1), and EVA Tools & Equipment; Outline the methods and procedures of EVA Preparation, EVA, and Post-EVA operations; Describe the Russian spacesuit used to perform an EVA; Provide a comparison between U.S. and Russian spacesuit hardware and EVA support; and Define the roles that different training facilities play in EVA training.

Moore, Sandra↗
DOE OSTI2022

ExaSGD: 2022 Kernel Thrust Activities

The Kernel Thrust milestone ADSE22-407 covers the development of device-capable optimization algorithms and solvers technologies required by the ExaSGD project’s software stack in order to solve security-constrained alternating current optimal power flow (SC-ACOPF) problems on emerging exascale architectures. To this extent, in FY22 the main objective of the Kernel Thrust was (i) provide sparse optimization solver that runs efficiently on hardware accelerator devices (i.e., NVIDIA and AMD GPUs) to perform intra-node computations, (ii) strengthen the reliability and increase the performance of the mixed-dense sparse (MDS) solver of HiOp for deployment on the FY22 target architectures, Summit and Crusher, and (iii) increase performance by improving the mathematical algorithm and refining the parallel MPI-based implementation of the coarse-grain parallel solver HiOp-PriDec for capabilities deployment on the FY22 target architectures, Summit and Crusher. This document presents the developments and contributions done by the Kernels Thrust Team in FY22 toward completion of the above-mentioned objectives. These contributions progressed along four main development (sub)thrusts: (1) Design and implementation of a sparse optimization solver for use on hardware accelerators; (2) Improvement of the mathematical algorithm and of the parallel implementation of HiOp-PriDec to ensure readiness and efficient coarse-grain parallelism for FY23 target exascale machine; and (3) Support Software and Application Development Thrusts of the exaSGD project in their deployment of the project’s software stack on AMD- and NVIDIA-based architectures. The development of the sparse optimization solver (thrust 1 above) was new in FY22 and resulted in a new sparse solver in HiOp (available as of version 0.6). The second development thrust was a continuation of the efforts from FY21 and improved the mathematical algorithm and the communication strategy of the HiOp-PriDec solver. The last developement thrust is a large collaborative effort. Namely, the project’s teams from multiple labs (LLNL, PNNL, ORNL, and NREL) performed large-scale demonstration of the ExaSGD software stack, namely the optimization solvers of HiOp interfaced with the modeling front-end ExaGO and the stochastic sampler PowerScenarios. These demonstration efforts solved large-scale instances of the SC-ACOPF challenge problem of medium network sizes (10, 000-bus system) and large number of contingencies on Summit (NVIDIA accelerators) and Crusher (AMD accelerators) systems at ORNL.

97 MATHEMATICS AND COMPUTING↗