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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

The SGI/Cray T3E: Experiences and Insights

The NASA Goddard Space Flight Center is home to the fifth most powerful supercomputer in the world, a 1024 processor SGI/Cray T3E-600. The original 512 processor system was placed at Goddard in March, 1997 as part of a cooperative agreement between the High Performance Computing and Communications Program's Earth and Space Sciences Project (ESS) and SGI/Cray Research. The goal of this system is to facilitate achievement of the Project milestones of 10, 50 and 100 GFLOPS sustained performance on selected Earth and space science application codes. The additional 512 processors were purchased in March, 1998 by the NASA Earth Science Enterprise for the NASA Seasonal to Interannual Prediction Project (NSIPP). These two "halves" still operate as a single system, and must satisfy the unique requirements of both aforementioned groups, as well as guest researchers from the Earth, space, microgravity, manned space flight and aeronautics communities. Few large scalable parallel systems are configured for capability computing, so models are hard to find. This unique environment has created a challenging system administration task, and has yielded some insights into the supercomputing needs of the various NASA Enterprises, as well as insights into the strengths and weaknesses of the T3E architecture and software. The T3E is a distributed memory system in which the processing elements (PE's) are connected by a low latency, high bandwidth bidirectional 3-D torus. Due to the focus on high speed communication between PE's, the T3E requires PE's to be allocated contiguously per job. Further, jobs will only execute on the user specified number of PE's and PE timesharing is possible but impractical. With a highly varied job mix in both size and runtime of jobs, the resulting scenario is PE fragmentation and an inability to achieve near 100% utilization. SGI/Cray has provided several scheduling and configuration tools to minimize the impact of fragmentation. These tools include PScheD (the political scheduler), GRM (the global resource manager) and NQE (the Network Queuing Environment). Features and impact of these tools will be discussed, as will resulting performance and utilization data. As a distributed memory system, the T3E is designed to be programmed through explicit message passing. Consequently, certain assumptions related to code design are made by the operating system (UNICOS/mk) and its scheduling tools. With the exception of HPF, which does run on the T3E, however poorly, alternative programming styles have the potential to impact the T3E in unexpected and undesirable ways. Several examples will be presented (preceeded with the disclaimer, "Don't try this at home! Violators will be prosecuted!")

Bernard, Lisa Hamet↗
DOE OSTI2018

T7 Expression Systems for Inducible Production of Proteins from Cloned Genes in E. coli

Inducible T7 expression systems are capable of producing a wide range of proteins in E. coli . Improvements over common practice include: preventing unintended induction by establishing and maintaining expression strains in non-inducing growth media comprised entirely of purified components instead of complex growth media that may variably induce target proteins on approach to saturation; and expressing many target proteins in parallel by convenient and productive auto-induction in BL21(DE3) and other suitable hosts, instead of IPTG induction. From earliest days, basal expression prevented establishment of inducible strains for producing proteins that are stressful to the host. Newly developed pAL vectors now reduce basal expression to levels where coding sequences for even the most stressful proteins can be maintained and induced. In conclusion, asymmetric ligation allows simple and efficient cloning of individual coding sequences or simultaneous cloning of two or three coding sequences for co expression from a single pAL vector.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2025

Kelvin–Helmholtz instability under stabilizing parallel magnetic field in nonhomogeneous compressible MHD flows

We study the Kelvin–Helmholtz instability (KHI) for the general case of a compressible, nonhomogeneous, magnetized plasma flow. The study is limited to a vortex sheet interface with an imposed parallel magnetic field. We introduce a new formalism based on a convective Mach number M c , a convective Alfvénic Mach number M Ac , and a total convective Mach number that combines the two. We derive an analytic expression of the KHI growth rate for a homogeneous flow (i.e., zero Atwood number, A=0) that converges toward both the expression for unmagnetized compressible flow and Chandrasekhar's expression for magnetized incompressible flow. Otherwise, the dispersion relation is solved numerically and allows deriving general stability diagrams of magnetized KHI for the triplet (A, M c , β −plasma) parameters. We show these parameters uniquely define all configurations for a parallel magnetic field. We also construct diagrams with respect to the convective Alfvénic Mach number, the β − plasma parameter, or the magnetic field showing which magnetic field strength is required for stabilizing a given shear flow. The theoretical growth rates are compared with 18 simulations made with the GAMERA code, currently used for 3D magnetospheric simulations. Finally, we apply our results to the analysis of a past KHI experiment performed at the OMEGA laser facility, showing linear theory succeeds to provide accurate estimates of the growth rate at early times. We further discuss how our results can inform future experiments in the high-Mach magnetized regime at the National Ignition Facility. Possible limitations of the study due to resistive, mixing, or turbulence effects are discussed.

compressible flows↗
DOE OSTI2023

KinCat v.1.0

SAND2024-02099O The software is designed to allow researchers to perform kinetic Monte Carlo (KMC) simulations of catalytic reactions on a 2D lattice. The code is written efficiently to run on a variety of shared memory computing architectures (e.g. GPU, multi-core) and to natively express the full complexity of lateral interactions on reaction rates. The software allows researchers to perform KMC simulations of catalytic reactions on a 2D lattice. It uses parallel shared-memory computing architectures to reduce run-times and allows for simultaneous simulation of multiple independent runs. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Najm, Habib↗
NASA NTRS1987

Exploiting loop level parallelism in nonprocedural dataflow programs

Discussed are how loop level parallelism is detected in a nonprocedural dataflow program, and how a procedural program with concurrent loops is scheduled. Also discussed is a program restructuring technique which may be applied to recursive equations so that concurrent loops may be generated for a seemingly iterative computation. A compiler which generates C code for the language described below has been implemented. The scheduling component of the compiler and the restructuring transformation are described.

Gokhale, Maya B.↗
NASA NTRS1995

SAMPEX special pointing mode

A new pointing mode has been developed for the Solar, Anomalous, and Magnetospheric Particle Explorer (SAMPEX) spacecraft. This pointing mode orients the instrument boresights perpendicular to the field lines of the Earth's magnetic field in regions of low field strength and parallel to the field lines in regions of high field strength, to allow better characterization of heavy ions trapped by the field. The new mode uses magnetometer signals and is algorithmically simpler than the previous control mode, but it requires increased momentum wheel activity. It was conceived, designed, tested, coded, uplinked to the spacecraft, and activated in less than seven months.

Markley, F. Landis↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1998

Heterogeneous Distributed Computing for Computational Aerosciences

The research supported under this award focuses on heterogeneous distributed computing for high-performance applications, with particular emphasis on computational aerosciences. The overall goal of this project was to and investigate issues in, and develop solutions to, efficient execution of computational aeroscience codes in heterogeneous concurrent computing environments. In particular, we worked in the context of the PVM[1] system and, subsequent to detailed conversion efforts and performance benchmarking, devising novel techniques to increase the efficacy of heterogeneous networked environments for computational aerosciences. Our work has been based upon the NAS Parallel Benchmark suite, but has also recently expanded in scope to include the NAS I/O benchmarks as specified in the NHT-1 document. In this report we summarize our research accomplishments under the auspices of the grant.

Sunderam, Vaidy S.↗
NASA NTRS1997

Turbomachinery Flows Modeled

Last year, researchers at the NASA Lewis Research Center used the average passage code APNASA to complete the largest three-dimensional simulation of a multistage axial flow compressor to date. Consisting of 29 blade rows, the configuration is typical of those found in aeroengines today. The simulation, which was executed on the High Performance Computing and Communications (HPCC) Program IBM SP2 parallel computer located at the NASA Ames Research Center, took nearly 90 hr to complete. Since the completion of this activity, a fine-grain, parallel version of APNASA has been written by a team of researchers from General Electric, NASA Lewis, and NYMA. Timing studies performed on the SP2 have shown that, with eight processors assigned to each blade row, the simulation time is reduced by a factor of six. For this configuration, the simulation time would be 15 hr. The reduction in computing time indicates that an overnight turnaround of a multistage configuration simulation is feasible. In addition, average passage forms of two-equation turbulence models were formulated. These models are currently being incorporated into APNASA.

Adamczyk, John J.↗
DOE OSTI2022

Assembling Multiphysics Nuclear Reactor Simulations Using the MOOSE Framework

The Multiphysics Object Oriented Simulation Environment (MOOSE) [1] is an open-source, parallel finite element framework which provides the foundation for many advanced modeling and simulation tools developed under the Department of Energy (DOE) Nuclear Energy Advanced Modeling and Simulation (NEAMS) Program [2] for the analysis of advanced reactors. The MOOSE framework provides the common foundational capability on which many NEAMS codes for reactor analysis are built. The MOOSE framework also includes several systems to assemble unique workflows and couplingamong MOOSE-based applications. In particular, the MultiApp and Transfer Systems are widely used to assemble different MOOSE-based or MOOSE-wrapped physics applications together to perform loosely or tightly coupled multiphysics simulations. The National Reactor Innovation Center (NRIC) Virtual Test Bed (VTB) [3] hosts publicly available nuclear reactor multiphysics simulation examples which leverage MOOSE’s MultiApp System to meet the modeling needs of different reactor types. The flexibility and robustness of coupling provided by MOOSE permits rapid development of coupled physics models for a wide range of reactor types and events

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2019

Computational and Experimental Benchmarking for Transient Fuel Testing

In 2018 the Transient Reactor Test (TREAT) Facility was restarted. This now-operational facility brings back world-class transient fuel testing capabilities to the U.S. Among a number of parallel efforts prior to the TREAT Facility’s restart a Department of Energy (DoE) Integrated Research Project (IRP) was funded for the purpose of benchmarking the TREAT with several goals in mind: To produce a comprehensive evaluation of existing TREAT Facility neutronics data using the next generation reactor core neutronics codes in accordance with established guidelines per the International Handbook of Evaluated Reactor Physics Benchmark Experiments (IRPhEP). To perform a benchmark using ready-use computational fluid dynamics tools against that of a historically collected sodium loop experiment collected in the TREAT. To design, develop and test a new experimental thermal hydraulic system of a representative TREAT Facility water flow loop. And benchmark the data collected against that produced via RELAP5-3D and TRACE. To develop a comprehensive instrumentation plan for the TREAT Facility by benchmarking performing of advanced in-pile instruments in the Massachusetts Institute of Technology Research Reactor (MITR) and the TREAT. The integrated team brought together collaborating members from three universities including Oregon State University (OSU), the University of Michigan (UM), and Massachusetts Institute of Technology (MIT); three national laboratories, Idaho National Laboratory, Argonne National Laboratory (ANL), and Oak Ridge National Laboratory (ORNL); and two industry partners, TerraPower (TP) and Harris Thermal Transfer Products (HTTP). A brief summary of accomplishments resulting from this IRP includes two filed patents, more than 40 conference papers, two published benchmark reports through IRPhEP, a new representative thermal hydraulic test facility alike the in-pile PWR water flow loop for TREAT and the first advanced instruments tested within the TREAT core upon its restart. The papers presented herein were developed and provide a summary of the significant technical accomplishments which align with the four project’s objectives. The collaborators has significant support from countless parties including the operational and technical staff at TREAT to ensure that their outcomes most impactfully aligned with program needs. Lastly the collaborators would like to acknowledge the fiscal support of the DoE’s Office of Nuclear Energy under work package identification number NU-15-OR-OSU- 0701-01. This report contains selected papers from the Computational and Experimental Benchmarking for Transient Fuel Testing Integrated Research Project.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗
DOE OSTI2022

Neural Networks for Nuclear Reactions in MAESTROeX

We demonstrate the use of neural networks to accelerate the reaction steps in the MAESTROeX stellar hydrodynamics code. A traditional MAESTROeX simulation uses a stiff ODE integrator for the reactions; here, we employ a ResNet architecture and describe details relating to the architecture, training, and validation of our networks. Our customized approach includes options for the form of the loss functions, a demonstration that the use of parallel neural networks leads to increased accuracy, and a description of a perturbational approach in the training step that robustifies the model. We test our approach on millimeter-scale flames using a single-step, 3-isotope network describing the first stages of carbon fusion occurring in Type Ia supernovae. We train the neural networks using simulation data from a standard MAESTROeX simulation, and show that the resulting model can be effectively applied to different flame configurations. This work lays the groundwork for more complex networks, and iterative time-integration strategies that can leverage the efficiency of the neural networks.

79 ASTRONOMY AND ASTROPHYSICS↗
NASA NTRS1993

Parallel solution of high-order numerical schemes for solving incompressible flows

A new parallel numerical scheme for solving incompressible steady-state flows is presented. The algorithm uses a finite-difference approach to solving the Navier-Stokes equations. The algorithms are scalable and expandable. They may be used with only two processors or with as many processors as are available. The code is general and expandable. Any size grid may be used. Four processors of the NASA LeRC Hypercluster were used to solve for steady-state flow in a driven square cavity. The Hypercluster was configured in a distributed-memory, hypercube-like architecture. By using a 50-by-50 finite-difference solution grid, an efficiency of 74 percent (a speedup of 2.96) was obtained.

Milner, Edward J.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS2000

MAP Algorithms for Decoding Linear Block Codes Based on Sectionalized Trellis Diagrams

The maximum a posteriori probability (MAP) algorithm is a trellis-based MAP decoding algorithm. It is the heart of turbo (or iterative) decoding that achieves an error performance near the Shannon limit. Unfortunately, the implementation of this algorithm requires large computation and storage. Furthermore, its forward and backward recursions result in long decoding delay. For practical applications, this decoding algorithm must be simplified and its decoding complexity and delay must be reduced. In this paper, the MAP algorithm and its variations, such as log-MAP and max-log-MAP algorithms, are first applied to sectionalized trellises for linear block codes and carried out as two-stage decodings. Using the structural properties of properly sectionalized trellises, the decoding complexity and delay of the MAP algorithms can be reduced. Computation-wise optimum sectionalizations of a trellis for MAP algorithms are investigated. Also presented in this paper are bidirectional and parallel MAP decodings.

Lui, Ye↗