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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,693 records · Page 94
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

A Novel Protection Scheme for Unbalanced Faults in Inverter Dominated Networks: A Computationally Efficient Algorithm for Entry-Level Relays

Microgrids are now a common practice in distribution systems to increase resilience and reliability. However, microgrid protection remains a critical challenge, considering its requirement to operate in both grid connected and islanded, and the variability in fault characteristics under each mode of operation. This paper presents unbalanced power (S unb ) based fault detection algorithm, which considers local voltage and current unbalances to determine faults in the system. S unb is a computationally efficient fault detection algorithm that is suitable for implementation in the programmable logic of entry level protective relays. In addition, the difference in current and voltage unbalance (D n ) is used to determine the fault type. The proposed method demonstrates high sensitivity and selectivity for line-to-ground (LG), line-to-line (LL), and double line-to-ground (LLG) faults, representing the most common faults in distribution systems. It also allows relay coordination with upstream and downstream protection devices in both island and grid connected operation, while preserving grading margins. The same pickup and time multiplier settings of a particular relay for both modes of operation eliminates the need for adaptive settings, which rely on communication networks. Validation was performed with a hardware-in-the-loop (HIL) setup using Typhoon HIL real time simulator interfaced with three entry-level, SEL 751 relays. Results confirmed the algorithm’s ability to discriminate fault conditions, and determine the fault type under both operating modes, maintain fast detection times, and ensure proper protection coordination.

fault classification↗
DOE OSTI2026

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗
DOE OSTI2019

Single-Submodule Open-Circuit Fault Diagnosis for a Modular Multi-level Converter Using Artificial Intelligent-based Techniques

Modular multi-level converters (MMCs) are one of the promising topologies in recent years for medium or high voltage applications. They are considered as the next generation DC/AC converters for medium/high voltage (MV/HV) motor drive applications due to their transform-less structures, high efficiency and modularity. Reliability is one of the most important challenges in MMCs, since a large number of power switching devices are used and each of these devices can be considered as a potential failure point. It is significant to detect and locate the fault accurately and apply appropriate protections in a timely manner. This paper investigates the behavior of the failure submodules and healthy submodules and use artificial neural network (ANN) classification algorithms for singlesubmodule open-circuit fault diagnosis. The ANN algorithm is implemented in field programmable gate array (FPGA) and the ANN parameters training is completed offline in Matlab. Experimental results of the proposed fault diagnosis for a singlemodule open-circuit fault are presented in this paper.

artificial intelligent↗
DOE OSTI2019

OPEN-CODE, REAL-TIME EMULATION TESTBED OF GRID-CONNECTED TYPE-3 WIND TURBINE SYSTEM WITH HARDWARE VALIDATION

This paper presents the design and development of an open-code Type-3 wind turbine virtual-testbed for real-time simulations. The proposed testbed includes the bare code for all the models required to emulate a Type-3 wind turbine system: the Doubly-Fed Induction Generator (DFIG) dynamic model, single-mass drive train, wind turbine system, and average model of the back to back power. This testbed can be executed in PC-layer for offline simulations or can be executed in real-time on the National Instruments (NI)-CompactRIO (cRIO) platform. The discrete-time models are implemented on the Field Programmable Gate Array (FPGA), using LabVIEW, and validated against a physical hardware setup. The emulated stator and rotor currents and DC-link voltage are compared against physical measurements creating a validated platform independent from third-party models and suitable for applications in real-time. The proposed testbed is intended to be available to researchers, wind turbine manufacturers, and utility companies to perform tests using a validated platform to verify proposed control designs of DFIG wind turbines.

Ferrari Maglia, Max↗
DOE OSTI2024

FTTN: Feature-Targeted Testing for Numerical Properties of NVIDIA & AMD Matrix Accelerators

While NVIDIA has been the dominant provider of GPUs for HPC and ML, now AMD has several offerings of GPUs. This encourages programmers to try out AMD GPUs for new codes and also port existing codes over. Unfortunately, without understanding the floating-point differences between these GPU types, software development or porting can introduce bugs—and currently such an understanding is lacking. The magnitude of this open question becomes clear if one imagines the the number of floating-point precision choices (FP16, FP32, etc.), floating-point formats (standard floats, brain-float, etc.), and execution units available (elementary units, matrix/tensor cores, etc.) Questions such as rounding modes and subnormal support are also important. Most of these answers are unknown today or are hard to access. We provide the first testing-guided approach that answers a significant number of these questions. We also devise tests to reveal internal information (e.g., extra bits kept) to make sure that our findings are reliable. Many of our tests employ systematically generated random-programs, others apply fast-math flags and some involve fused multiplyadd. Especially for tensor/matrix cores, the tests have nontrivial logic that we present Our testing approach is reusable for the plethora of GPUs yet to be introduced. Our findings include up to 7 ulps of difference between NVIDIA and AMD for sin and cos at FP32 precision and 3 ulp at FP64. In our study of matrix cores (NVIDIA) and tensor cores (AMD), we have extensively characterized rounding modes (truncation versus round-to-nearest), the number of extra internal bits kept (whether 3 bits are kept or not), subnormal support for inputs and outputs across four different floating-point formats and across NVIDIA A100 and AMD MI250X GPUs. We believe that this wealth of data becoming available for the first time may help avoid significant porting bugs when migrating code across these platforms.

Li, Xinyi↗
DOE OSTI2024

CHARM-SYCL & IRIS: A Tool Chain for Performance Portability on Extremely Heterogeneous Systems

Performance portability is becoming crucial as high-performance computing systems become increasingly heterogeneous. We have many options for CPUs and accelerators (e.g., GPUs) but also for non-Von Neumann architectures such as field-programmable gate arrays. This paper presents the CHARM-SYCL unified programming environment for multiple accelerator types as a performance-portable programming environment. It uses the IRIS library developed at Oak Ridge National Laboratory as the back end accelerator runtime. IRIS has a high-performance scheduler to distribute tasks across accelerators. This design allows us to run an application from the same source on multiple systems with multiple configurations. We provide three types of portability with CHARM-SYCL: Portable Workflow, Compiler and Runtime Portability, and Application and Performance Portability. We implement a Monte Carlo simulation benchmark code on the CHARM-SYCL execution environment and demonstrate that our programming environment can accommodate extremely heterogeneous systems.

Fujita, Norihisa↗
DOE OSTI2019

A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based TDC for Low Power and Low Resource Usage Applications

In common digital electronics design practice, combinatorial loop is less preferable, especially in the multi-bit cases. An exception of multi-bit feedback system that is allowed to be implemented in combinatorial loop is the Gray code sequence generator. The Gray code sequence generator runs by itself without being driven by an external clock. It steps through Gray code sequence significantly faster than the Gray code counter under the same silicon technology. In high energy physics experiments, it is necessary to find a low resource usage and low power TDC (Time-to-Digital-Converter) scheme for high channel count detectors. A Gray code oscillator based TDC is a good candidate for such a scheme. In this paper, we describe our work of design and implementation of a TDC based on combinatorial Gray code oscillator in a Xilinx Kintex-7 FPGA (Field-Programmable Gate Array). The implementation and test results are presented. The test result shows that the TDC using only 8 logic elements is able to reach a RMS precision of 160 ps for time difference measurements of a single pulse. The single pulse measurement precision can be further improved to 51 ps with the weighted average scheme using data from the same TDC channels captured by 4 consecutive system clock edges.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2018

Advanced Photovoltaic Inverter Control Development and Validation in a Controller-Hardware-in-the-Loop Test Bed

Penetration of solar photovoltaic (PV) installations into the grid has increased in recent years. In the past, photovoltaic installations have not included grid-support functionality. Grid support functions including Volt-VAR (VVAR), Frequency-Watt (FW), Volt-Watt (VW), frequency/voltage-ride through, as well as other inverter functions such as anti-islanding are recommended by standards such as IEEE 1547 to allow PV inverters to contribute to acceptable operation and stability of distribution systems with high penetrations of PV and to ensure predictable response of the PV inverters. First, low-level and high-level grid support inverter control functions were developed and tested in simulation. The developed controller is able to integrate advanced controller functions in a coordinated approach, avoiding any conflict between the different control objectives. The algorithms were then programmed on an off-the-shelf embedded controller that included a dual-core CPU and FPGA. The details of the high-level grid support function and the lower level switching control will be presented. Second, this programmed controller is tested using a controller-hardware-in-the-loop (CHIL) test bed setup using an FPGA-based real-time simulator. The CHIL setup has the capability to run at a 500 nano-second time-step to accommodate the 20 kHz switching frequency of the developed controller. The advanced control function and CHIL test bed details provided here will aide future researchers to design, implement, and test advanced inverter functions for PV inverters.

14 SOLAR ENERGY↗
DOE OSTI2022

Power Electronic Hardware-in-the-Loop (PE-HIL): Testing Individual Controllers in Large-Scale Power Electronics Systems

Large power electronics systems like multi-port autonomous reconfigurable solar power plant (MARS) are increasingly being researched upon to integrate emerging energy sources. MARS connects photovoltaic (PV) systems and energy storage systems (ESSs) to high-voltage direct current (HVdc) links/grids and high-voltage alternating current (ac) transmission grids. As these large power electronics systems incorporate complex hierarchical control systems that are close-by and communicate fast, the control systems require an unique power electronic hardware-in-the-loop (PE-HIL) real-time architecture to evaluate individual controllers. In this paper, a PE-HIL real-time architecture is proposed to evaluate one of the hundreds to thousands of digital signal processors (DSPs) that are a part of the complex hierarchical control system. The DSP connects to a central processing unit (CPU) and a field programmable gate array (FPGA) that form a part of the upper levels of the control system. The DSP is part of the lower level of the control system. The proposed PE-HIL architecture is tested and evaluated. Preliminary test results are presented to showcase the concept.

Debnath, Suman↗
DOE OSTI2023

Strengthening Cybersecurity for Industrial Control Systems: Innovations in Protecting PLC-Based Infrastructure

In this paper, we propose two new approaches aimed at enhancing the security of industrial control systems (ICS) that utilize programmable logic controllers (PLCs) for the control of critical processes. The first approach involves the addition of a unique digital watermark to the PWM control that adjusts the motor speed to control the critical process. This enables efficient detection and identification of any unauthorized modifications to the sensor signals responsible for controlling the plant. The second approach focuses on monitoring the input current (i.e power) drawn by the PLC during the execution of critical process control tasks. Malicious intrusions to change the PLC parameters and/or unauthorized firmware updates can be rapidly detected. Both approaches demonstrate a substantial improvement in the security of ICS, effectively safeguarding against potential cyber-attacks. Experimental results from a laboratory scale water tank level controlled via PLC showcases rapid intrusion detection capabilities.

Huang, Peng-Hao↗
DOE OSTI2025

Enabling Scientific Applications with Performance-Portability and High-Productivity for Multi-GPU Programming with JACC.Multi

This work bridges the gap between multi-GPU computing and high-productivity, performance-portable programming solutions. Our goal is to enhance scientific applications with a productive and portable solution—program once, deploy everywhere—for multi-GPU programming with no cost to programmability. To accomplish this, we implemented JACC.Multi, which is part of the Julia for ACCelerators (JACC) performance-portable framework. JACC. Multi is the only high-level, portable metaprogramming solution that targets multi-GPU environments and is integrated in a readily accessible programming language (e.g., Julia language). With transparent GPU-to-GPU communication, JACC. Multi is optimized for scientific application workloads and is portable for NVIDIA and AMD accelerators. For the evaluation, we use two modern multi-GPU systems: Hudson, which features two NVIDIA H100 Hopper GPUs per node, and Frontier, which features four AMD MI250X GPUs per node, each with two Graphics Compute Dies (GCDs) for a total of eight GCDs per node. Additionally, as part of the evaluation, we use JACC (one GPU), MPI+JACC, and JACC. Multi codes that implement well-known and widely used scientific algorithms/kernels such as the conjugate gradient algorithm and an explicit forward Euler solver that requires GPU-to-GPU communication. Overall, JACC. Multi codes achieve better performance than MPI+JACC codes and significant speedups over JACC (one GPU), with up to 1.9× on Hudson and 6× on Frontier.

Valero Lara, Pedro [ORNL] (ORCID:0000000214794310)↗
DOE OSTI2025

Flexible Operation of Microgrids Through Operator-Configurable Microgrid Controllers

Microgrids are becoming critical assets in power distribution systems. This is partly due to the resiliency and reliability challenges faced by power distribution systems in the last decade and partly due to the increased integration of distributed energy resource assets, such as solar photovoltaic. This increased need for microgrids has created a multitude of needs for microgrid controllers. Most microgrid controllers in the past decade have been uniquely programmed or custom programmed to meet the needs of a specific microgrid. Currently, IEEE standards aim to integrate the needs and capabilities of microgrid controllers under a unified umbrella. But the standards do not recommend necessary or appropriate software development practices for microgrid controllers. In addition, the programmable nature and maintenance of controllers are also key characteristics that fall outside the coverage of the standards. In this paper, we present the best software practices that utility engineers and microgrid operators should consider in the microgrid software platform. This paper can be used as an information document for developing documentation of controller requirements and assessing microgrid controller requirements.

Banshee microgrid↗
DOE OSTI2022

DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit data streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across application kernels. However, emerging streaming applications at the edge (scientific instruments, sensor networks, network processing) perform much more than digital signal processing and often are data and input dependent. This leads to extremely variable kernel execution times, severely impacting the throughput of the entire pipeline if resources are only statically allocated. Therefore, in this paper, we propose DRIPS — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We present a unified compiler framework to facilitate the mapping of a given streaming application onto the DRIPS CGRA architecture. The experimental results show that DRIPS achieves an average throughput improvement of 1.46$\times$ across a set of representative applications over a statically partitioned solution. The additional area overhead to enable dynamic rebalancing consumes 16.34% of the entire area for a 5x5 CGRA prototype.

Tan, Cheng↗
DOE OSTI2023

IRIS-DMEM: Efficient Memory Management for Heterogeneous Computing

This paper proposes an efficient data memory management approach for the Intelligent RuntIme System (IRIS) heterogeneous computing framework along with new data transfer policies. IRIS provides a task-based programming model for extreme heterogeneous computing (e.g., CPU, GPU, DSP, FPGA) with support for today's most important programming languages (e.g., OpenMP, OpenCL, CUDA, HIP, OpenACC). However, the IRIS framework either forces the programmer to introduce data transfer commands for each task or relies on suboptimal memory management for automatic and transparent data transfers. The work described here extends IRIS with novel heterogeneous memory handling and introduces novel data transfer policies by employing the Distributed data MEMory handler (DMEM) for efficient and optimal movement of data among the various computing resources. The proposed approach achieves performance gains of up to 7× for tiled LU factorization and tiled DGEMM (i.e., matrix multiplication) benchmarks. Moreover, this approach also reduces data transfers by up to 71% when compared to previous IRIS heterogeneous memory management handlers. This work compares the performance results of the IRIS framework's novel DMEM with the StarPU runtime and MAGMA math library for GPUs. Experiments show a performance gain of up to 1.95× over StarPU and 2.1× over MAGMA.

Miniskar, Narasinga Rao↗
DOE OSTI2019

Detecting Sensors and Inferring their Relations at Level-0 in Industrial Cyber-Physical Systems

While there exist tools and techniques to discover, identify, map, and analyze cyber physical components at higher levels of the cyber space, there is a lack of capabilities to reach down to the sensors at the bottom-most levels, such as levels 0 and 1 of the Purdue Enterprise Reference Model for cyber-physical systems (CPS). Conventional information technology (IT)-based tools reach as far as the network-side of programmable logic controllers, but are inadequate to access and analyze the physical side of the CPS infrastructure that directly interfaces with the actual physical processes and systems. In this paper, we present our research and development efforts aimed at addressing this gap, by building a system called Deep-cyberia (Deep Cyber-Physical System Interrogation and Analysis) that incorporates algorithms and interfaces aimed at uncovering sensors and computing estimates of correlations among them.

Perumalla, Kalyan↗
DOE OSTI2018

Two-Layer Predictive Controller for V2G and G2V Services Using on Wireless Power Transfer Technology

This paper presents a comprehensive solution that allows electric vehicles (EV) to autonomously charge and discharge their batteries wirelessly during long term parking and/or the transient stops. A two-layer power-flow controller for bidirectional wireless power transfer system (BWPTS) in EVs applications is proposed. The proposed controller can manage the bidirectional power-flow between EV and surrounding infrastructures such as power grid, home microgrid, building micro-grid, road or another vehicle. It consists of two levels of control; the first is responsible for communicating with the surrounding infrastructures and gathering information from driver, charging station, power grid and battery management system and then, based on these information, it estimates the EV's psychological price as a function of its battery's state-of-charge (SOC) and compares it with the energy price to decide whether to charge, discharge or abstain, and how much the charging or discharging rate. The second layer receives the reference signal from the first one and generates the control parameters for two synchronized resonant converters (one is on the vehicle side and the other is on the grid side) to provide the requited power-flow. The proposed controller is adaptively estimating the system parameters to consider the misalignment conditions effects on the system performance. The parameter estimation is achieved using only one voltage sensor. The second layer control is designed based on a new analytical modeling for the power flow in the system. For verification purposes, a prototype for BWPTS was built and driven by the proposed controller, which was implemented using a field-programmable gate array (FPGA) integrated circuit. The proposed controller provides very fast and stable response during both the transient and steady state operation in comparison with the conventional PI controller.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2021

PLC-based Impedance Measurement and Current Injection Response Analysis

Studying and mitigating the vulnerabilities of Programmable Logic Controllers (PLCs) to electromagnetic pulse is important for the reliability of the power system. In this paper, an effective impedance measurement scheme is proposed to estimate the susceptibility of PLCs to an electromagnetic pulse. The equivalent non-uniform transmission line model is established to eliminate the impact of the fixture in the de-embedding process. Based on the measured impedance, the equivalent circuit is established to calculate the response of the device when subjected to the electromagnetic pulse. The voltage and current responses of different interfaces are compared utilizing the developed pulse Current Injection (CI) method. Finally, the impedance measurement scheme is verified through testing using three measuring instruments. And the CI simulation experiments reveal the characteristics and susceptibilities of different PLCs interfaces, indicating that some protection measures are required for the reliable operation of PLC.

Qiu, Wei↗
DOE OSTI2021

DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across kernels. However, streaming applications often are data-dependent, leading to variable kernel execution times depending on the input data and impacting the throughput of the entire pipeline if resources are statically allocated. Therefore, in this paper, we discuss the design of DynPaC — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We discuss the required software and hardware components to manage partial dynamic reconfiguration. We demonstrate that by supporting partial dynamic reconfiguration, we can obtain an average speedup of 1.44X for a representative set of applications w.r.t. static partitioning, with a limited area overhead (6.4% of the entire chip).

Tan, Cheng↗