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All sources NASA NTRS DOE OSTI

DOE OSTI2016

Development of flexible, scalable, low cost readout for beam tests of the high granularity calorimeter for the CMS endcap

As part of the development of the High Granularity Calorimeter for the CMS Endcap at HL-LHC, The CMS collaboration is conducting a comprehensive series of beam tests. The first beam test, with a single HGC module was carried out in March of 2016 at the Fermilab Test Beam Facility, continuing to a 16 module test in July of 2016. We describe here the development of a low cost readout system that is simple to implement and is able to grow with the system under test. The system is based on the low cost Zynq SoC that allows simple DAQ development in a Linux environment. For this application we used the Digilent ZedBoard, which allows high speed LVDS links and Linux software development on a single commercial board. A small custom FPGA board designed to comply with the VITA 57 Field Programmable Mezzanine Card standard implements the interface to the readout ASIC mounted on the HGC sensor modules and provides the LVDS links to the ZedBoard, either directly over the FMC connector or via a custom carrier card. This architecture provides scalability, ease of development and low cost.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2021

Case Study of Using Kokkos and SYCLs Performance-Portable Frameworks for Milc-Dslash Benchmark on NVIDIA, AMD and Intel GPUs

Six of the top ten supercomputers in the TOP500 list from June 2021 rely on NVIDIA GPUs to achieve their peak compute bandwidth. With the announcement of Aurora, Frontier, and El Capitan, Intel and AMD have also entered the domain of providing GPUs for scientific computing. A consequence of the increased diversity in the GPU landscape is the emergence of portable programming models such as Kokkos, SYCL, OpenCL, and OpenMP, which allow application developers to maintain a single-source code across a diverse range of hardware architectures. While the portable frameworks try to optimize the compute resource usage on a given architecture, it is the programmers responsibility to expose parallelism in an application that can take advantage of thousands of processing elements available on GPUs. In this paper, we introduce a GPU-friendly parallel implementation of Milc-Dslash that exposes multiple hierarchies of parallelism in the algorithm. Milc-Dslash was designed to serve as a benchmark with highly optimized matrix-vector multiplications to measure the resource utilization on the GPU systems. The parallel hierarchies in the Milc-Dslash algorithm are mapped onto a target hardware using Kokkos and SYCL programming models. We present the performance achieved by Kokkos and SYCL implementations of Milc-Dslash on NVIDIA A100 GPU, AMD MI100 GPU, and Intel Gen9 GPU. Additionally, we compare the Kokkos and SYCL performances with those obtained from the versions written in CUDA and HIP programming models on NVIDIA A100 GPU and AMD MI100 GPU, respectively.

Dufek, Amanda S↗

DOE OSTI2018

Comparison of Doubly-Fed Induction Generator Machine Models for Real-Time Simulations

This work presents a detailed comparison among three implementations of the Doubly-Fed Induction Generator (DFIG) machine model. The alpha-beta-gamma, synchronous (dqo), and natural frame dynamic machine models were deployed on a Field-Programmable Gate Array (FPGA) and compared in terms of execution time and resource utilization. These machine models were also validated against a physical DFIG machine during balanced and unbalanced grid conditions. A benchmark is presented with the objective of selecting the machine model, orientation and state-space representation that is best suited for real-time simulations. The selected machine model is used to develop a real-time emulator of a Type-3 wind system. This emulator enables the study of wind turbine system in realtime using a validated platform while allowing controller testing without relying on expensive third-party solutions.

Ferrari Maglia, Max↗

DOE OSTI2025

A High-Current Pulsed Prototype Power Supply

The Accelerator Controls Operations Research Network (ACORN) project aims to modernize the accelerator control system and replace aging power supplies at Fermilab. As part of this effort, outdated RF ferrite bias power supplies will be redesigned. These power supplies are essential for tuning the resonant frequency of RF cavities by delivering programmable current outputs of up to 2500 A and voltages ranging from −10 V to +35 V. They operate at a repetition rate of 15 Hz in the Booster ring, and 1 Hz at the Main Injector ring. The power supplies utilize a bank of transistors in the linear region, connected in parallel with the load, to actively regulate the output current from a 12-pulse SCR bridge. To support this upgrade, a new bias power supply topology was developed as proof of concept. The design utilizes an IGBT Hbridge operating in Pulse Width Modulation (PWM) mode, controlled by a microcontroller. A prototype, constructed using spare components, successfully delivered an output current of 500 A at a repetition rate of 15 Hz during initial testing. The circuit's bandwidth was measured at 480 Hz, highlighting opportunities for further optimization in the controller design to achieve the target bandwidth of 2 kHz.

Bullman, Austin [ORNL]↗

DOE OSTI2020

IEEE 1547-2018 Based Interoperable PV Inverter with Advanced Grid-Support Functions

Grid integration of photovoltaic (PV) inverters has been increasing in the past decade. As a result of the uncertainties introduced with high penetrations of PV, better monitoring and control of the PV inverters becomes crucial for improving overall system stability. This paper focuses on the communications capability of the inverter controller and on enabling interoperability. Multiple standards are available to enable interoperability in PV inverters. In this paper, an interoperable controller, enabled by Distributed Network Protocol 3 (DNP3) communications protocols, is developed for a grid-connected, three-phase PV inverter. The DNP3 server for the PV inverter is programmed on the real-time layer of the field-programmable gate array (FPGA)-based inverter controller. Set points for advanced inverter control functions, such as volt/VAr curves, ride-through curves, are sent from a DNP3 client, a simulated distribution management system application, to the PV inverter through DNP3. This communications capability of the inverter controller is validated using a controller-hardware-in-the-loop experimental setup. The code developed to achieve the interoperability is available in the public domain through open-source software licensing. This interoperability will enable smoother grid integration of smart PV inverters with advanced grid-support functions as well as allow better monitoring and control of PV inverters for grid stability.

14 SOLAR ENERGY↗

DOE OSTI2021

Consensus International Solar Resource Standards and Best Practices Development

Standardization and best practices of data sets and models enable the industry to develop widely accepted protocols adapted to various stages of solar project development and operations. In collaboration with the International Energy Agency Photovoltaic Power Systems Programme Task 16, the National Renewable Energy Laboratory (NREL) developed and regularly updates the Best Practices Handbook for the Collection and Use of Solar Resource Data for Solar Energy Applications. In collaboration with ASTM's radiometry subcommittee, NREL leads the development of various radiometric standards. These contribute to increased accuracy in the measurement of the solar resource available to conversion systems and boost the development and improvement of radiative models. These models can then provide the long-term geographic or climatic distribution of solar radiation for areas where measured solar data are not available. Further, these standards play a preeminent role in all aspects of solar energy projects, including standard conditions, methods and instrumentation, accelerated testing, and service lifetime of materials.

ASTM↗

DOE OSTI2020

Extending XACC for Quantum Optimal Control

Quantum computing vendors are beginning to open up application programming interfaces for direct pulse-level quantum control. With this, programmers can begin to describe quantum kernels of execution via sequences of arbitrary pulse shapes. This opens new avenues of research and development with regards to smart quantum compilation routines that enable direct translation of higher-level digital assembly representations to these native pulse instructions. In this work, we present an extension to the XACC system-level quantum-classical software framework that directly enables this compilation lowering phase via user-specified quantum optimal control techniques. This extension enables the translation of digital quantum circuit representations to equivalent pulse sequences that are optimal with respect to the backend system dynamics. Our work is modular and extensible, enabling third party optimal control techniques and strategies in both C++ and Python. We demonstrate this extension with familiar gradient-based methods like gradient ascent pulse engineering (GRAPE), gradient optimization of analytic controls (GOAT), and Krotov's method. Our work serves as a foundational component of future quantum-classical compiler designs that lower high-level programmatic representations to low-level machine instructions.

Nguyen, Thien↗

DOE OSTI2024

AutoCheck: Automatically Identifying Variables for Checkpointing by Data Dependency Analysis

Checkpoint/Restart (C/R) has been widely deployed in numerous HPC systems, Clouds, and industrial data centers, which are typically operated by system engineers. Nevertheless, there is no existing approach that helps system engineers without domain expertise and domain scientists without system fault tolerance knowledge identify those critical variables accounted for correct application execution restoration in a failure for C/R. To address this problem, we propose an analytical model and a tool (AutoCheck) that can automatically identify critical variables to checkpoint for C/R. AutoCheck relies on first, analytically tracking and optimizing data dependency between variables and other application execution state, and second, a set of heuristics that identify critical variables for checkpointing from the refined data dependency graph (DDG). AutoCheck allows programmers to pinpoint critical variables to checkpoint quickly within a few minutes. We evaluate AutoCheck on 13 representative HPC benchmarks, demonstrating that AutoCheck can efficiently identify correct critical variables to checkpoint.

HPC↗

DOE OSTI2016

Development of ROACH firmware for microwave multiplexed X-ray TES microcalorimeters

We are developing room temperature electronics based upon the ROACH platform for reading out microwave multiplexed X-ray TES. ROACH is an open-source hardware and software platform featuring a large Xilinx Field Programmable Gate Array (FPGA), Power PC processor, several 10GB Ethernet SFP+ interfaces, and a collection of daughter boards for analog signal generation and acquisition. The combination of a ROACH board, ADC/DAC conversion daughter boards, and hardware for RF mixing allows for the generation and capture of multiple RF tones for reading out microwave multiplexed x-ray TES microcalorimeters. The FPGA is used to generate multiple tones in base band, from 10MHz to 250MHz, which are subsequently mixed to RF in the multiple GHz range and sent through the microwave multiplexer. The tones are generated in the FPGA by storing a large lookup table in Quad Data Rate (QDR) SRAM modules and playing out the waveform to a DAC board. Once the signal has been modulated to RF, passed through the microwave multiplexer, and has been modulated back to base band, the signal is digitized by an ADC board. The tones are modulated to 0Hz by using a FPGA circuit consisting of a polyphase filter bank, several Xilinx FFT blocks, Xilinx CORDIC blocks (for converting to magnitude and phase), and special phase accumulator circuit for mixing to exactly 0Hz. Upwards of 256 channels can be simultaneously captured and written into a bank of 256 First-In-First-Out (FIFO) memories, with each FIFO corresponding to a channel. Individual channel data can be further processed in the FPGA before being streamed through a 10GB Ethernet fiber-optic interface to a Linux system. The Linux system runs software written in Python and QT C++ for controlling the ROACH system, capturing data, and processing data.

Firmware↗

DOE OSTI2017

Progress on the Development of the Nb 3 Sn 11T Dipole for the High Luminosity Upgrade of LHC

The high-luminosity large hadron collider (LHC) project at CERN entered into the production phase in October 2015 after the completion of the design study phase. In the meantime, the development of the 11 T dipole needed for the upgrade of the collimation system of the machine made significant progress with very good performance of the first two-in-one magnet model of 2-m length made at CERN. The 11 T dipole, which is more powerful than the current main dipoles of LHC, can be made shorter with an equivalent integrated field. This will allow creating space for the installation of additional collimators in specific locations of the dispersion suppressor regions. Following tests carried out during heavy ions runs of LHC in the end of 2015, and a more recent review of the project budget, the installation plan for the 11 T dipole was revised. Consequently, one 11 T dipole full assembly containing two 11 T dipoles of 5.5-m length will be installed on either side of interaction point 7. These two units shall be installed during the long shutdown 2 in years 2019-2020. After a brief reminder on the design features of the magnet, this paper describes the current status of the development activities, in particular the short model programme and the construction of the first full scale prototype at CERN. Finally, critical operations such as the reaction treatment and the coil impregnation are discussed, the quench performance tests results of the two-in-one model are reviewed and finally, the plan toward the production for the long shut down 2 is described.

43 PARTICLE ACCELERATORS↗

DOE OSTI2017

Automating High-Precision X-Ray and Neutron Imaging Applications with Robotics

Los Alamos National Laboratory and the University of Texas at Austin recently implemented a robotically controlled nondestructive testing (NDT) system for X-ray and neutron imaging. This system is intended to address the need for accurate measurements for a variety of parts and, be able to track measurement geometry at every imaging location, and is designed for high-throughput applications. This system was deployed in a beam port at a nuclear research reactor and in an operational inspection X-ray bay. The nuclear research reactor system consisted of a precision industrial seven-axis robot, 1.1-MW TRIGA research reactor, and a scintillator-mirror-camera-based imaging system. The X-ray bay system incorporated the same robot, a 225-keV microfocus X-ray source, and a custom flat panel digital detector. The robotic positioning arm is programmable and allows imaging in multiple configurations, including planar, cylindrical, as well as other user defined geometries that provide enhanced engineering evaluation capability. The imaging acquisition device is coupled with the robot for automated image acquisition. The robot can achieve target positional repeatability within 17 μm in the 3-D space. Flexible automation with nondestructive imaging saves costs, reduces dosage, adds imaging techniques, and achieves better quality results in less time. Specifics regarding the robotic system and imaging acquisition and evaluation processes are presented. In conclusion, this paper reviews the comprehensive testing and system evaluation to affirm the feasibility of robotic NDT, presents the system configuration, and reviews results for both X-ray and neutron radiography imaging applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2018

An FPGA-Based Voltage Balancing Control for Multi-HV-IGBTs in Series Connection

The series connection of insulated gate bipolar transistors (IGBTs) allows operation at voltage levels higher than the rated voltage of one IGBT and has less power semiconductor costs compared to multilevel topologies. However, voltage unbalance during the switching transient is a challenge for series-connected device application. This paper presents an field-programmable gate array (FPGA)-based voltage balancing strategy for multiseries-connected high-voltage (HV)-IGBTs including an FPGA-based active voltage balancing control (AVBC) circuit integrated into the gate driver and the control for multiseries-connected IGBTs. As a result, the effectiveness of the control has been experimentally validated in a prototype using four 4.5 kV HV-IGBTs in series connection.

42 ENGINEERING↗

DOE OSTI2017

Blocker-tolerant and high-sensitivity $Δ$\!$Σ$ correlation digitizer for radar and coherent receiver applications

In this study, a coherent subsampling digitizer for pulsed Doppler radar systems is proposed. Prior to transmission, the radar system modulates the RF pulse with a known pseudorandom binary phase shift keying (BPSK) sequence. Upon reception, the radar digitizer uses a programmable sample-and-hold circuit to multiply the received waveform by a properly time-delayed version of the known a priori BPSK sequence. This operation demodulates the desired echo signal while suppressing the spectrum of all in-band noncorrelated interferers, making them appear as noise in the frequency domain. The resulting demodulated narrowband Doppler waveform is then subsampled at the IF frequency by a delta-sigma modulator. Because the digitization bandwidth within the delta-sigma feedback loop is much less than the input bandwidth to the digitizer, the thermal noise outside of the Doppler bandwidth is effectively filtered prior to quantization, providing an increase in signal-to-noise ratio (SNR) at the digitizer's output compared with the input SNR. In this demonstration, a delta-sigma correlation digitizer is fabricated in a 0.18-μm CMOS technology. The digitizer has a power consumption of 1.12 mW with an IIP3 of 7.5 dBm. The digitizer is able to recover Doppler tones in the presence of blockers up to 40 dBm greater than the Doppler tone.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2019

FELIX-Based Readout of the Single-Phase ProtoDUNE Detector

Large liquid argon (LAr) time projection chambers (TPCs) have been adopted for the Deep Underground Neutrino Experiment (DUNE) experiment's far detector, which will be composed of four 17-kton detectors situated 1.5 km underground at the Sanford Underground Research Facility. This represents a large increase in scale compared to existing experiments. Both single- and dual-phase technologies will be validated at CERN, in cryostats capable of accommodating full-size detector modules, and exposed to low-energy charged particle beams. This program, called ProtoDUNE, also allows for extensive tests of data acquisition strategies. The Front-End LInk eXchange (FELIX) readout system was initially developed within the ATLAS collaboration and is based on custom field-programmable gate array (FPGA)-based Peripheral Component Interconnect Express input/output cards, connected through point-to-point links to the detector front end and hosted in commodity servers. FELIX will be used in the single-phase ProtoDUNE setup to read the data coming from 2560 anode wires organized in a single anode plane assembly (APS) structure. With a continuous readout at a sampling rate of 2 MHz, the system must deal with an input rate of 96 Gb/s. An external trigger will preselect time windows of 5 ms with interesting activity expected inside the detector. Event building will occur for triggered events, at a target rate of 25 Hz; the readout system will form fragments from the data samples matching the time window, carry out lossless compression, and forward the data to event building nodes over 10-Gb/s Ethernet. This paper discusses the design and implementation of this readout system as well as the first operational experience.

47 OTHER INSTRUMENTATION↗

DOE OSTI2021

A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network (NN) autoencoder model can be implemented in a radiation-tolerant application-specific integrated circuit (ASIC) to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the Compact Muon Solenoid (CMS) experiment at the CERN Large Hadron Collider. The advantage of the machine learning approach is in the flexibility and configurability of the algorithm. By changing the NN weights, a unique data compression algorithm can be deployed for each sensor in different detector regions and changing detector or collider conditions. To meet area, performance, and power constraints, we perform quantization-aware training to create an optimized NN hardware implementation. The design is achieved through the use of high-level synthesis tools and the hls4ml framework and was processed through synthesis and physical layout flows based on a low-power (LP)-CMOS 65-nm technology node. The flow anticipates 200 Mrad of ionizing radiation to select gates and reports a total area of 3.6 mm 2 and consumes 95 mW of power. The simulated energy consumption per inference is 2.4 nJ. Furthermore, this is the first radiation-tolerant on-detector ASIC implementation of an NN that has been designed for particle physics applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2021

Enabling Scalable and Extensible Memory-mapped Datastores in Userspace

Exascale workloads are expected to incorporate data-intensive processing in close coordination with traditional physics simulations. These emerging scientific, data-analytics and machine learning applications need to access a wide variety of datastores in flat files and structured databases. Programmer productivity is greatly enhanced by mapping datastores into the application process's virtual memory space to provide a unified “in-memory” interface. Currently, memory mapping is provided by system software primarily designed for generality and reliability. However, scalability at high concurrency is a formidable challenge on exascale systems. Also, there is a need for extensibility to support new datastores potentially requiring HPC data transfer services. In this article, we present UMap , a scalable and extensible userspace service for memory-mapping datastores. Furthermore, through decoupled queue management, concurrency aware adaptation, and dynamic load balancing, UMap enables application performance to scale even at high concurrency. We evaluate UMap in data-intensive applications, including sorting, graph traversal, database operations, and metagenomic analytics. Our results show that UMap as a userspace service outperforms an optimized kernel-based service across a wide range of intra-node concurrency by 1.22-1.9 × . We performed two case studies to demonstrate UMap 's extensibility. First, a new datastore residing in remote memory is incorporated into UMap as an application-specific plugin. Second, we present a persistent memory allocator Metall built atop UMap for unified storage/memory.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2024

Object Proxy Patterns for Accelerating Distributed Applications

Workflow and serverless frameworks have empowered new approaches to distributed application design by abstracting compute resources. However, their typically limited or one-size-fits-all support for advanced data flow patterns leaves optimization to the application programmer—optimization that becomes more difficult as data become larger. The transparent object proxy, which provides wide-area references that can resolve to data regardless of location, has been demonstrated as an effective low-level building block in such situations. Here we propose three high-level proxy-based programming patterns—distributed futures, streaming, and ownership—that make the power of the proxy pattern usable for more complex and dynamic distributed program structures. We motivate these patterns via careful review of application requirements and describe implementations of each pattern. As a result, we evaluate our implementations through a suite of benchmarks and by applying them in three meaningful scientific applications, in which we demonstrate substantial improvements in runtime, throughput, and memory usage.

Distributed Computing↗

DOE OSTI2024

Numerical Simulation of Irradiation Induced Swelling for STAR 4.1 Blanket

Here, this article presents the preliminary results of FEM implementation of irradiation-induced swelling, hardening, and creep effect using ANSYS user programmable features (UPFs) applied to material properties. The first liquid metal breeding blanket model for STAR 4.1 tokamak as a part of the virtual prototyping system is under development at Princeton Plasma Physics Laboratory (PPPL). Intense neutron irradiation produces significant changes in the physical and mechanical properties of Fe-(8%–9%)Cr-based reduced activation ferritic martensitic (RAFM) steels. An ANSYS model of the breeding blanket was built to involve these irradiation-induced material property changes with neutron fluence distribution mapped from the MCNP model. Simulation results show that significant structure deformation forms from nuclear swelling, stress, and plastic strain arising from DPA gradient through wall thickness. The material degradation effect is not negligible. This modeling feature can either assist in analyzing the structural behaviors with the influence of nuclear swelling or provide guidance to design the structure to withstand irradiation.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗