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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Non-Micropipe Dislocations in 4H-SiC Devices: Electrical Properties and Device Technology Implications

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vectors greater than or equal to 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = 1c with no hollow core) in densities on the order of thousands per sq cm, nearly 100-fold micropipe densities. While not nearly as detrimental to SiC device performance as micropipes, it has recently been demonstrated that elementary screw dislocations somewhat degrade the reverse leakage and breakdown properties of 4H-SiC p(+)n diodes. Diodes containing elementary screw dislocations exhibited a 5% to 35% reduction in breakdown voltage, higher pre-breakdown reverse leakage current, softer reverse breakdown I-V knee, and microplasmic breakdown current filaments that were non-catastrophic as measured under high series resistance biasing. This paper details continuing experimental and theoretical investigations into the electrical properties of 4H-SiC elementary screw dislocations. The nonuniform breakdown behavior of 4H-SiC p'n junctions containing elementary screw dislocations exhibits interesting physical parallels with nonuniform breakdown phenomena previously observed in other semiconductor materials. Based upon experimentally observed dislocation-assisted breakdown, a re-assessment of well-known physical models relating power device reliability to junction breakdown has been undertaken for 4H-SiC. The potential impact of these elementary screw dislocation defects on the performance and reliability of various 4H-SiC device technologies being developed for high-power applications will be discussed.

Neudeck, Philip G.↗
NASA NTRS1998

Breakdown Degradation Associated with Elementary Screw Dislocations in 4H-SiC P(+)N Junction Rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector greater than 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = lc with no hollow core) in densities on the order of thousands per sq cm, nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current-voltage (I-V) characteristics of 4H-SiC p(+)n diodes. First, Synchrotron White Beam X-ray Topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p(+)n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I-V knee, and no visible concentration of breakdown current. In contrast devices that contained at least one elementary screw dislocation exhibited a 5% to 35% reduction in breakdown voltage, a softer breakdown I-V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.

Neudeck, P. G.↗
NASA NTRS1999

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (< 250 V) 4H-SiC p(sup +)n Junction Diodes--Part II: Dynamic Breakdown Properties: Dynamic Breakdown Properties - Part 2

This paper outlines the dynamic reverse-breakdown characteristics of low-voltage (<250 V) small-area <5 x 10(exp -4) sq cm 4H-SiC p(sup +)n diodes subjected to nonadiabatic breakdown-bias pulsewidths ranging from 0.1 to 20 microseconds. 4H-SiC diodes with and without elementary screw dislocations exhibited positive temperature coefficient of breakdown voltage and high junction failure power densities approximately five times larger than the average failure power density of reliable silicon pn rectifiers. This result indicates that highly reliable low-voltage SiC rectifiers may be attainable despite the presence of elementary screw dislocations. However, the impact of elementary screw dislocations on other more useful 4H-SiC power device structures, such as high-voltage (>1 kV) pn junction and Schottky rectifiers, and bipolar gain devices (thyristors, IGBT's, etc.) remains to be investigated.

Neudeck, Philip G.↗
NASA NTRS1998

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (less than 250 V) 4H-SiC p(+)n Junction diodes: DC Properties - Part 1

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = 1c with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4)/sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS1999

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (<250 V) 4H-SiC p+n Junction Diodes - Part 1: DC Properties

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = lc with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4) sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS2002

Confinement of Screw Dislocations to Predetermined Lateral Positions in (0001) 4H-SiC Epilayers Using Homoepitaxial Web Growth

This paper reports initial demonstration of a cantilevered homoepitaxial growth process that places screw dislocations at predetermined lateral positions in on-axis 4H-SiC mesa epilayers. Thin cantilevers were grown extending toward the interior of hollow pre-growth mesa shapes etched into an on-axis 4H-SiC wafer, eventually completely coalescing to form roofed cavities. Each completely coalesced cavity exhibited either: 1) a screw dislocation growth spiral located exactly where final cantilever coalescence occurred, or 2) no growth spiral. The fact that growth spirals are not observed at any other position except the central coalescence point suggests that substrate screw dislocations, initially surrounded by the hollow portion of the pre-growth mesa shape, are relocated to the final coalescence point of the webbed epilayer roof. Molten potassium hydroxide etch studies revealed that properly grown webbed cantilevers exhibited no etch pits, confirming the superior crystal quality of the cantilevers.

Neudeck, Philip G.↗
NASA NTRS1998

Perimeter Governed Minority Carrier Lifetimes in 4H-SiC p+n Diodes Measured by Reverse Recovery Switching Transient Analysis

Minority carrier lifetimes in epitaxial 4H-SiC p-n junction diodes were measured via an analysis of reverse recovery switching characteristics. Behavior of reverse recovery storage time (t(sub s)) as a function of initial ON-state forward current (I(sub f)) and OFF-state reverse current (I(sub R)) followed well-documented trends which have been observed for decades in silicon p-n rectifiers. Average minority carrier (hole) lifetimes (tau(sub p)) calculated from plots of t(sub s) vs I(sub R)/I(sub F) strongly decreased with decreasing device area. Bulk and perimeter components of average hole lifetimes were separated by plotting tau(sub p) as a function of device perimeter-to-area ratio (P/A). This plot reveals that perimeter recombination is dominant in these devices, whose areas are all less than 1 square mm. The bulk minority carrier (hole) lifetime extracted from the 1/Tau(sub p) vs P/A plot is approximately 0.7 microns, well above the 60 ns to 300 ns average lifetimes obtained when perimeter recombination effects are ignored in the analysis. Given the fact that there has been little previous investigation of bipolar diode and transistor performance as a function of perimeter-to-area ratio, this work raises the possibility that perimeter recombination may be partly responsible for poor effective minority carrier lifetimes and limited performance obtained in many previous SiC bipolar junction devices.

Neudeck, Philip G.↗
NASA NTRS1998

Perimeter Governed Minority Carrier Lifetimes in 4H-SiC p(+)-n Diodes Measured by Reverse Recovery Switching Transient Analysis

Minority carrier lifetimes in epitaxial 4H-SiC p(+)-n junction diodes were measured via an analysis of reverse recovery switching characteristics. Behavior of reverse recovery storage time (t(s)) as a function of initial ON-state forward current (I(F)) and OFF-state reverse current (I(R)) followed well-documented trends which have been observed for decades in silicon p-n rectifiers. Average minority carrier (hole) lifetimes (tau(p)) calculated from plots of t(s) vs I(R)/I(F) strongly decreased with decreasing device area. Bulk and perimeter components of average hole lifetimes were separated by plotting 1/tau(p) as a function of device perimeter-to- area ratio (P/A). This plot reveals that perimeter recombination is dominant in these devices, whose areas are all less than 1 sq mm. The bulk minority carrier (hole) lifetime extracted from the 1/tau(p) vs P/A plot is approximately 0.7 micro-s, well above the 60 ns to 300 ns average iit'eptimes obtained when perimeter recombination effects are ignored in the analysis. Given the fact that there has been little previous investigation of bipolar diode and transistor performance as a function of perimeter-to-area ratio, this work raises the possibility that perimeter recombination may be partly responsible for poor effective minority carrier lifetimes and limited performance obtained in many previous SiC bipolar junction devices.

Neudeck, Philip G.↗
NASA NTRS2001

Low Temperature Ohmic Contact Formation of Ni2Si on N-type 4H-SiC and 6H-SiC

Nickel Silicide (Ni2Si) is investigated as possible ohmic contact to heavily nitrogen-doped N-type 4H-SiC and 6H-SiC. Nickel Silicide was deposited via electron gun with various thicknesses on both Si and C faces of the SiC substrates. The Ni2Si contacts were formed at room temperature as well as at elevated temperatures (400 to 1000 K). Contact resistivities and I-V characteristics were measured at temperatures between 100 and 700 C. To investigate the electric properties, I-V characteristics were studied and the Transmission Line Method (TLM) was used to determine the specific contact resistance for the samples at each annealing temperature. Both Rutherford Backscattering Spectroscopy (RBS) and Auger Electron Spectroscopy (AES) were used for depth profiling of the Ni2Si, Si, and C. X-ray Photoemission Spectroscopy (XPS) was used to study the chemical structure of the Ni2Si/SiC interface.

Elsamadicy, A. M.↗
NASA NTRS2003

Measured Propagation Characteristics of Coplanar Waveguide on Semi-Insulating 4H-SiC Through 800 K

Wireless sensors for high temperature industrial applications and jet engines require RF transmission lines and RF integrated circuits (RFICs) on wide bandgap semiconductors such as SiC. In this paper, the complex propagation constant of coplanar waveguide fabricated on semiinsulating 4H-SiC has been measured through 813 K. It is shown that the attenuation increases 3.4 dB/cm at 50 GHz as the SiC temperature is increased from 300 K to 813 K. Above 500 K, the major contribution to loss is the decrease in SiC resistivity. The effective permittivity of the same line increases by approximately 5 percent at microwave frequencies and 20 percent at 1 GHz.

Ponchak, George E.↗
NASA NTRS2002

Glennan Microsystems Initiative

During the 2001-2002 award period, we performed research on Pt/Ti/bare 6H-SiC and bare 4H-SiC interfaces in order to identify their electronic properties as a function of surface preparation. The overall aim of this work is to optimize the electronic properties of metal contacts to SiC as well as the active SiC material itself as a function of surface preparation and subsequent processing. Initially, this work has involved identifying bare surface, subsurface, and metal induced gap states at the metal-SiC contact and correlating energies and densities of deep levels with Schottky barrier heights. We used low energy electron-excited nanoluminescence (LEEN) spectroscopy, X-ray photoemission spectroscopy (XPS), and Secondary Ion Mass Spectrometry (SIMS) in order to correlate electronic states and energy bands with chemical composition, bonding, and crystal structure. A major development has been the discovery of polytype transformations that occur in 4H-SiC under standard microelectronic process conditions used to fabricate SiC devices. Our results are consistent with the stacking fault generation, defect formation, and consequent degradation of SiC recently reported for state-of-the-art ABB commercial diodes under localized electrical stress. Our results highlight the importance of -optimizing process conditions and material properties - anneal times, temperatures and doping to control such structural changes within epitaxial SiC layers. Thus far, we have established threshold times and temperatures beyond which 4H-SiC exhibits 3C-SiC transformation bands for a subset of dopant concentrations and process conditions. On the basis of this temperature time behavior, we have been able to establish an activation energy of approximately 2.5 eV for polytype transformation and dislocation motion. Work continues to establish the fundamental mechanisms underlying the polytype changes and its dependence on material parameters.

Brillson, Leonard J.↗
NASA NTRS1996

Effect of Tilt Angle on the Morphology of SiC Epitaxial Films Grown on Vicinal (0001) SiC Substrates

In this study of 4H-SiC and 6H-SiC epitaxial films we found that film morphology was strongly dependent on the tilt angle of the substrate. Large surface steps (up to 25 nm high) due to step bunching were more prevalent at smaller tilt angles. Also, 4H films were more susceptible than 6H to 3C-SiC inclusions during growth. The lateral growth of steps from screw dislocations in low-tilt-angle substrates demonstrated that step bunching on the atomic scale was anisotropic with respect to growth direction for both 4H-SiC and 6H-SiC. A model explaining this behavior is presented. We observed and directly measured the Burgers vector of a 'super' screw dislocation in a 6H-SiC epilayer.

Powell, J. A.↗
NASA NTRS1997

Process-Induced Morphological Defects in Epitaxial CVD Silicon Carbide

Silicon carbide (SiC) semiconductor technology has been advancing rapidly, but there are numerous crystal growth problems that need to be solved before SiC can reach its full potential. Among these problems is a need for an improvement in the surface morphology of epitaxial films that are grown to produce device structures. Various processes before and during epilayer growth lead to the formation of morphological defects observed in SiC epilayers grown on SiC substrates. In studies of both 6H and 4H-SiC epilayers, atomic force microscopy (AFM) and other techniques have been used to characterize SiC epilayer surface morphology. In addition to the well-known micropipe defect, SiC epilayers contain growth pits, triangular features (primarily) in 4H-SiC, and macro step due to step bunching. In work at NASA Lewis, it has been found that factors contributing to the formation of some morphological defects include: defects in the substrate bulk, defects in the substrate surface caused by cutting and polishing the wafer, the tilt angle of the wafer surface relative to the basal plane, and growth conditions. Some of these findings confirm results of other research groups. This paper presents a review of published and unpublished investigations into processes that are relevant to epitaxial film morphology.

Powell, J. A.↗
NASA NTRS1998

Gaseous Etching for Characterization of Structural Defects in Silicon Carbide Single Crystals

Single crystal SiC substrates were subjected to high-temperature H2/C3H8 gaseous etches. The etches resulted in a variety of surface features on 4H-SiC substrates that included elongated hillocks from 10 to more than 100 microns in length by a few microns in width. In some 4H- and 6H-SiC substrates, the etches resulted in a continuous coverage of macrosteps. We conclude that the morphology observed after the etching process is influenced by the local Si-C bilayer stacking sequence on the surface of off-(0001)oriented substrates. A model is presented for the formation of the hillocks, based on localized transformations of the 4H substrates during the high temperature etch process.

Powell, J. A.↗
NASA NTRS2001

Ab-Initio Description and Prediction of Properties of Carbon-Based and Other Non-Metallic Materials

We have resolved the long-standing problem consisting of 30%-50% theoretical underestimates of the band gaps of non-metallic materials. We describe the Bagayoko, Zhao, and Williams (BZW) method that rigorously circumvents the basis-set and variational effect presumed to be a cause of these underestimates. We present ab-initio, computational results that are in agreement with experiment for diamond (C), silicon (Si), silicon carbides (3C-SiC and 4H-SiC), and other semiconductors (GaN, BaTiO3, AlN, ZnSe, ZnO). We illustrate the predictive capability of the BZW method in the case of the newly discovered cubic phase of silicon nitride (c-Si3N4) and of selected carbon nanotabes [(10,0), and (8,4)]. Our conclusion underscores the inescapable need for the BZW method in ab-initio calculations that employ a basis set in a variational approach. Current nanoscale trends amplify this need. We estimate that the potential impact of applications of the BZW method in advancing our understanding of nonmetallic materials, in informing experiment, and particularly in guiding device design and fabrication is simply priceless.

Bagayoko, D.↗
NASA NTRS2002

Method for Growing Low-Defect Single Crystal Heteroepitaxial Films

A method is disclosed for growing high-quality low-defect crystal films heteroepitaxially on substrates that are different than the crystal films. The growth of the first two heteroepitaxial bilayers is performed on a first two-dimensional nucleate island before a second growth of two-dimensional nucleation is allowed to start. The method is particularly suited for the growth of 3C-SiC, 2H-AlN, or 2H-GaN on 6H-SiC, 4H-SiC, or silicon substrates.

Powell, J. Anthony↗
NASA NTRS2002

Growth of Defect-Free 3C-Sic on 4H- and 6H-SIC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3C-SiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (Delta/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS2001

Growth of Defect-Free 3C-SiC on 4H- and 6H-SiC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3CSiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (delta a/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗