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Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis
The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field (E eƒƒ ) on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be E$^{-1.8}_{eƒƒ}$ and E$^{-2.4}_{eƒƒ}$, respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of E eƒƒ in controlling the value of channel mobility in 4H-SiC MOSFETs.
A Comparison of Ion Implantation at Room Temperature and Heated Ion Implantation on the Body Diode Degradation of Commercial 3.3 kV 4H-SiC Power MOSFETs
It has been demonstrated that basal plane dislocations (BPDs)-induced stacking faults (SFs) cause body diode degradation in commercial 4H-SiC power MOSFETs, especially with higher voltage ratings. BPDs originate from 4H-SiC boule, epi growth, and ion implantation. Considering the lower cost of ion implantation at room temperature (RT), this work investigates the potential of RT ion implantation replacing heated (HT) ion implantation by comparing the influence of both ion implantations on the body diode degradation of commercial 3.3 kV 4H-SiC power MOSFETs. We demonstrate with long-term (up to 1000 hours) forward current stress that RT implantation can keep the body diode degradation of 3.3 kV 4H-SiC power MOSFETs within the specification limits compared with HT implantation.
Mechanisms of Heavy Ion-Induced Single Event Burnout in 4H-SiC Power MOSFETs
This describes the mechanisms behind the failure of 4H-SiC Power MOSFETs when struck by a heavy ion. The modeled device is designed to simulate a commercially available 1200 V power MOSFET and the ion simulated is a silver ion with a Linear Energy Transfer of 46 MeV-cm2/mg commonly used in single event effect (SEE) testing. The device is shown in simulation to fail near 500 V, which is in close agreement to experiments. These simulations go to show that the failure of SiC MOSFET occurs near the interface between the epi and substrate layers due to the rapid increase of the electric field in that region and destruction of the device from impact ionization. From this, two designs were proposed and investigated that would help to mitigate the electric field in these regions and improve the device's tolerance to single-event burnout (SEB). The new designs increased the voltage at which SEB occurs from 500 V to over 900 V and increased the Ron,sp by only 5%.
Mesoplasma Formation and Thermal Destruction in 4H-SiC Power MOSFET Devices under Heavy Ion Bombardment
Investigation into mesoplasma formation from heavy ion strike in 4H-SiC power MOSFETs. Simulations involving the time evolution of several parameters have determined that the formation of a mesoplasma occurs deep within the epi of the device. Various physical parameters were investigated, and only thermal conductivity affected mesoplasma formation.
Investigation of the Effect of Gate Oxide Screening with Adjustment Pulse on Commercial SiC Power MOSFETs
This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation.
High temperature characteristics of nitric oxide annealed p-channel 4H-SiC metal oxide semiconductor field effect transistors
In this work, p-channel 4H-SiC MOSFETs were fabricated and analyzed at high temperature. It is demonstrated that nitridation of the gate oxide enables enhancement mode operation in these devices. Nitrogen incorporation at the 4H-SiC/SiO2 interface by nitric oxide annealing reduces the interface trap density energetically located in the lower half of the 4H-SiC bandgap, resulting in viable high temperature p-channel devices. In the 27–300 °C temperature range, the threshold voltage decreases with increasing temperature, consistent with the reduction of occupied interface traps at higher temperatures. The hole channel mobility is weakly temperature dependent under strong inversion conditions. Hall measurements support that above the threshold voltage, the mobility is limited by surface roughness scattering. In weaker inversion, the channel conductivity is limited by interface hole trapping and Coulomb scattering. In addition, high temperature bias stress measurements confirm a temperature activated hole trapping under negative gate bias, which requires further investigations.
Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs
Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.
Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability
To this day, trapezoidal defects are found in clusters and high counts in wafers representing the industry standard in terms of material quality being produced. This study sheds light on the nature, origin, behavior, and impact of this defect on device yield and reliability. Trapezoidal defects in 4H-SiC epitaxial layers were investigated by photoluminescence (PL) imaging, scanning electron microscopy (SEM), cathodoluminescence spectrum imaging (CLSI), SEM electron beam induced current (EBIC) imaging, and by transmission electron microscopy (TEM) observation. The bar-shaped stacking faults were identified by the PL and CL measurements with a peak emission wavelength of 420 and 450 nm. An optoelectronic behavioral study based on the recombination enhanced dislocation glide mechanism revealed how expanding dislocations and stacking faults interact with each other. Combining the luminescence and microscopy results, the nature of the stacking faults was identified as being a combination of Shockley-type and Frank-type stacking faults. The TEM analysis showed that these defects originate from the substrate and the stacking sequences of some of the faults were determined as (…2, 4, 2…) and (…2, 3, 2…) in the Zhdanov's notation by high-resolution TEM. The origin of this defect is speculated based on our results and previous reports. The EBIC imaging showed that the high density of SFs in these towers is a strong site of carrier recombination, which presumably has an impact on the transfer characteristics of SiC devices. Furthermore, these defects have shown to impact metal oxide semiconductor field effect transistors electrical performance via an increase in the on-state resistance depending on the coverage percentage of the tower of defects in the active area of the device.
Nondestructive microstructural investigation of defects in 4H-SiC epilayers using a multiscale luminescence analysis approach
The development of metal oxide semiconductor field effect transistors (MOSFETs) utilizing epitaxially grown 4H-SiC has accelerated in recent years due to their favorable properties, including a high breakdown field, high saturated electron drift velocity, and good thermal conductivity. However, extended defects in epitaxial 4H-SiC can affect both device yields and operational lifetime. In this work, we demonstrate the importance of a multiscale luminescence characterization approach to studying nondestructively extended defects in epitaxial 4H-SiC semiconducting materials. Multiscale luminescence analysis reveals different aspects of excess charge carrier recombination behavior based on the scale of a particular measurement. Combining measurements of the same extended defect area at different scales tells us more about the essential nature of that defect and its microstructure. Here, we use photoluminescence imaging and cathodoluminescence spectrum imaging to investigate the recombination behavior of several different types of extended defects, including stacking faults, inclusions, and basal plane dislocations. A detailed understanding of the optoelectronic properties of extended defects in epitaxial SiC helps elucidate the microstructure of extended defects and can provide pathways to mitigate detrimental changes during device operation related to their evolution, such as the recombination enhanced dislocation glide effect that affects SiC-based MOSFETs.
Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs
This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (V th ) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as V th shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.
SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)
This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.
Electric Drive Technologies Consortium (EDTC)/ Cost competitive, high-Performance, highly Reliable (CPR) Power Devices on 4H-SiC (Final Report)
4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.
Switching Characteristics of a 1.2 kV, 50 mΩ SiC Monolithic Bidirectional Field Effect Transistor (BiDFET) with Integrated JBS Diodes
—The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.