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The Jet Propulsion Laboratory (JPL) is currently assessing the use of Area Array Packaging (AAP) for National Aeronautics and Space Administration (NASA) spaceflight applications. this work is being funded through NASA Headquarters, Code Q. The paper discusses background of AAP, objectives, and uses of AAP.
High density PWB (printed wiring board) with microvia technology is required for implementation of high density and high I/O area array packages (AAP). COTS (commercial off-the-shelf) AAP packaging technologies in high reliability versions with 1.27 mm pitch are now being considered for use in a number of NASA systems including Space Shuttle and Mars Rovers. NASA functional system designs are requiring more and more dense AAP packages and board space, which makes board microvia technology very attractive for effectively routing a large number of package inputs/outputs. However, the reliability of the fine feature microvias including via in pads is unknown for space applications. Understanding process and QA (quality assurance) indicators for reliability are important for low risk insertion of these newly available packages and PWBs. This paper presents literature search as well as test results for a high density board subjected to various thermal cycle and reflow profiles representative of tin-lead and lead-free solder reflow. Microvias sizes ranged from two to six mil with and without filling. Daisy chain microvias monitored during the test and PWBs were cross-sectioned to determine failure and locations. Optical and SEM photographs as well as resistance changes during cycling and Tg/Td (glass transition/decomposition temperature) characterisations are presented.
The Jet Propulsion Laboratory (JPL) is currently assessing the use of Area Array Packaging (AAP).
The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.