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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Time-multiplexed, optically-addressed, gigabit optical crossbar switch

A time-multiplexed, optically-addressed, crossbar switch (38) is provided using a two-dimensional, optically-addressed, reflective spatial light modulator (O-SLM) (20). Since the optical addressing is time-multiplexed, only N addressing lines are required for an N.times.N crossbar, rather than the N.sup.2 lines needed in the prior art. This reduction in addressing lines makes possible the development of enormous crossbar switches, such as 100.times.100, for the first time. In addition, since data paths remain entirely in the optics domain, data speeds can reach the multi-gigabit level. In the switch, a row (40) of N inputs (42) at the read wavelength is spread over one axis of the O-SLM. The light is refocused along the other axis to an output array (48) of detectors (50), so that each input has the potential to talk to any one output. The O-SLM is normally off, i.e., non-reflective, so that the output is, in the absence of an input signal, zero. A one-dimensional array (52) of lasers (54) at the write wavelength is imaged onto the O-SLM. Each laser scans across an entire row of the O-SLM; where the laser is on, it turns on a portion of the O-SLM and establishes a connection between a particular input and a particular output. A full row is scanned in a time much shorter than the response time of the O-SLM, so that state of the O-SLM is capacitively stored and dynamically refreshed. The scanning is accomplished by tuning the wavelength of the laser and passing it through a grating, which sweeps the beam in space.

Lang, Robert J.↗
NASA NTRS1992

Address tracing of parallel systems via TRAPEDS

Trace-driven simulation is an important aid in performance analysis of computer systems. Capturing address traces to use in these simulations, however, is a difficult problem for parallel processor architectures. A technique termed TRAPEDS modifies executable code (at the assembly language level) to dynamically collect the address trace from executing code. TRAPEDS has recently been implemented on both a hypercube multicomputer and a shared-memory multiprocessor. Particular attention is focused on strategies for efficiently and accurately collecting traces from both classes of parallel machines. The iPSC/2 hypercube multicomputer implementation traces both user and system code, and performs simulation on-the-fly to avoid large storage costs. Strategies are detailed for mitigating address trace distortion when collecting operating system traces. The Encore Multimax multiprocessor implementation uses a timer-based approach to reflect the interleaving of the processor traces and stores the traces to disc. Time and space overhead results are presented for both TRAPEDS implementations. Experimental cache simulation results derived from iPSC/2 address traces are presented to illustrate the importance of tracing operating system references.

Stunkel, Craig B.↗
NASA NTRS1991

Collecting address traces from parallel computers

Trace driven simulation is a well-established method of performance analysis for single processor computer systems. However, efficient and accurate memory address tracing for parallel computer systems is not well understood. In this paper we present a critical survey of recently implemented approaches to address tracing and highlight the issues specific to collection of traces for both shared and distributed memory parallel computers. These issues include potential distortion of the relative ordering of events by the address tracing activity, realistic interleaving of addresses generated by multiple processors, and I/O and storage problems associated with collecting traces for large parallel systems. The strengths and weaknesses of the parallel tracing approaches are described.

Stunkel, Craig B.↗
NASA NTRSDate not supplied

Automated Addressing Failure Detection for Multiplexer Systems

Multiplexers are electronic devices which select between several input signals and deliver an output signal. Also known as data selectors or mux, multiplexers are commonly used in circuit design to provide signal switching, simplify hardware and manufacturing, and decrease cost. Systems which use a digital mux as a switch or selector are vulnerable to events called addressing failures, arising in hardware or software. An addressing failure results in the system requesting, or the mux delivering, a data signal other than the one intended. The unintended use of this erroneous signal may lead to system-level failures. This paper discusses a novel method of automatic detection for addressing failures, utilizing multiplexer channelization and a monitoring algorithm.

multiplexer↗
NASA NTRS1981

Potential effects of the introduction of the discrete address beacon system data link on air/ground information transfer problems

This study of Aviation Safety Reporting System reports suggests that benefits should accure from implementation of discrete address beacon system data link. The phase enhanced terminal information system service is expected to provide better terminal information than present systems by improving currency and accuracy. In the exchange of air traffic control messages, discrete address insures that only the intended recipient receives and acts on a specific message. Visual displays and printer copy of messages should mitigate many of the reported problems associated with voice communications. The problems that remain unaffected include error in addressing the intended recipient and messages whose content is wrong but are otherwise correct as to format and reasonableness.

Grayson, R. L.↗
NASA NTRS1989

Evaluating local indirect addressing in SIMD proc essors

In the design of parallel computers, there exists a tradeoff between the number and power of individual processors. The single instruction stream, multiple data stream (SIMD) model of parallel computers lies at one extreme of the resulting spectrum. The available hardware resources are devoted to creating the largest possible number of processors, and consequently each individual processor must use the fewest possible resources. Disagreement exists as to whether SIMD processors should be able to generate addresses individually into their local data memory, or all processors should access the same address. The tradeoff is examined between the increased capability and the reduced number of processors that occurs in this single instruction stream, multiple, locally addressed, data (SIMLAD) model. Factors are assembled that affect this design choice, and the SIMLAD model is compared with the bare SIMD and the MIMD models.

Middleton, David↗
NASA NTRS2005

ALI (Autonomous Lunar Investigator): Revolutionary Approach to Exploring the Moon with Addressable Reconfigurable Technology

Addressable Reconfigurable Technology (ART) based structures: Mission Concepts based on Addressable Reconfigurable Technology (ART), originally studied for future ANTS (Autonomous Nanotechnology Swarm) Space Architectures, are now being developed as rovers for nearer term use in lunar and planetary surface exploration. The architecture is based on the reconfigurable tetrahedron as a building block. Tetrahedra are combined to form space-filling networks, shaped for the required function. Basic structural components are highly modular, addressable arrays of robust nodes (tetrahedral apices) from which highly reconfigurable struts (tetrahedral edges), acting as supports or tethers, are efficiently reversibly deployed/stowed, transforming and reshaping the structures as required.

Clark, P. E.↗
NASA NTRS1988

Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation

A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.

Buehler, Martin G.↗
NASA NTRS2017

Sensitivity Analysis Method to Address User Disparities in the Analytic Hierarchy Process

Decision makers often face complex problems, which can seldom be addressed well without the use of structured analytical models. Mathematical models have been developed to streamline and facilitate decision making activities, and among these, the Analytic Hierarchy Process (AHP) constitutes one of the most utilized multi-criteria decision analysis methods. While AHP has been thoroughly researched and applied, the method still shows limitations in terms of addressing user profile disparities. A novel sensitivity analysis method based on local partial derivatives is presented here to address these limitations. This new methodology informs AHP users of which pairwise comparisons most impact the derived weights and the ranking of alternatives. The method can also be applied to decision processes that require the aggregation of results obtained by several users, as it highlights which individuals most critically impact the aggregated group results while also enabling to focus on inputs that drive the final ordering of alternatives. An aerospace design and engineering example that requires group decision making is presented to demonstrate and validate the proposed methodology.

Marie Ivanco↗
NASA NTRSDate not supplied

Integrating Earth Observations and Socioeconomic Data to Address Health, Equity, and Environmental Justice

Access to reliable data about the characteristics of populations is a crucial component of decision making, policy development, and the assessment of progress towards strategic goals. Social determinants of health provide insight into the status of social and economic conditions within populations that have profound effects on public health, equity, and vulnerability. International frameworks such as the Sustainable Development Goals (SDGs) fundamentally focus on equality, but to efficiently address targets and indicators, socioeconomic data and Earth observations must be integrated to help identify populations most vulnerable to the impacts of climate change, natural disasters, health disparities, and poor policy planning. The ability to identify vulnerable populations with data analysis has the potential to empower community stakeholders with spatial awareness needed to inform decision-making that addresses equity and environmental justice issues within their communities. The EPA defines environmental justice (EJ) as “the fair treatment and meaningful involvement of all people regardless of race, color, national origin, or income with respect to the development, implementation and enforcement of environmental laws, regulations and policies.” NASA’s Earth Science Division (ESD) recognizes the benefits that Earth observations with NASA satellites create by equipping individuals with the knowledge to address community challenges. NASA’s Socioeconomic Data and Applications Center (SEDAC) supports the integration of socioeconomic and Earth science data as an “informational gateway.” This integration of data is advancing health, equity, and environmental justice initiatives.

Natasha Johnson-Griffin↗
NASA NTRS1981

User's guide for CCT2WA (converting CCT's to work-addressable file)

The CCT2WA program, developed to convert the shuttle post-flight computer compatible tape data to a word addressable mass storage file, is described. The use of utility processors that can be used to copy word addressable files from mass storage to mass storage is also described.

Williams, S. D.↗
NASA NTRS1988

Frequency addressable beams for land mobile communications

Satellites used for mobile communications need to serve large numbers of small, low cost terminals. The most important parameters affecting the capacity of such systems are the satellite equivalent isotropically radiated power (EIRP) and gain to noise temperature ratio (G/T) and available bandwidth. Satellites using frequency addressed beams provide high EIRP and G/T with high-gain antenna beams that also permit frequency reuse over the composite coverage area. Frequency addressing is easy to implement and compatible with low-cost terminals and offers higher capacity than alternative approaches.

Thompson, J. D.↗
NASA NTRS1989

Optical Addressing And Clocking Of RAM's

Proposed random-access-memory (RAM) addressing system, in which memory linked optically to read/write logic circuits, greatly increases computer operating speed. System - comprises addressing circuits including numerous lasers as signal sources, numerous optical gates including optical detectors associated with memory cells, and holographic element to direct light signals to desired memory-cell locations - applied to high-capacity digital systems, supercomputers, and complex microcircuits.

Johnston, Alan R.↗
NASA NTRS1989

Indirect addressing and load balancing for faster solution to Mandelbrot Set on SIMD architectures

SIMD computers with local indirect addressing allow programs to have queues and buffers, making certain kinds of problems much more efficient. Examined here are a class of problems characterized by computations on data points where the computation is identical, but the convergence rate is data dependent. Normally, in this situation, the algorithm time is governed by the maximum number of iterations required by each point. Using indirect addressing allows a processor to proceed to the next data point when it is done, reducing the overall number of iterations required to approach the mean convergence rate when a sufficiently large problem set is solved. Load balancing techniques can be applied for additional performance improvement. Simulations of this technique applied to solving Mandelbrot Sets indicate significant performance gains.

Tomboulian, Sherryl↗
NASA NTRS1989

Analysis of hypercube cache performance using address traces generated by TRAPEDS

The authors utilize a recently developed software method of capturing and analyzing address traces, known as TRAPEDS (TRAce Producing Execution Driven Simulation), to provide address traces for cache performance evaluation on a hypercube multicomputer. Utilizing TRAPEDS user code traces obtained from the implementations of several parallel algorithms on the Intel iPSC/2 hypercube, the authors simulate the cache performance effects of changing cache size, line size, and set associativity. Particular attention is devoted to the effect on cache performance of changing the dimension of the hypercube for a particular program and to the variation in cache statistics among the nodes of the hypercube.

Stunkel, Craig B.↗
NASA NTRS1991

Addressable-Matrix Integrated-Circuit Test Structure

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

Sayah, Hoshyar R.↗
NASA NTRS1991

Address tracing for parallel machines

Recently implemented parallel system address-tracing methods based on several metrics are surveyed. The issues specific to collection of traces for both shared and distributed memory parallel computers are highlighted. Five general categories of address-trace collection methods are examined: hardware-captured, interrupt-based, simulation-based, altered microcode-based, and instrumented program-based traces. The problems unique to shared memory and distributed memory multiprocessors are examined separately.

Stunkel, Craig B.↗