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Results for “Analog-to-Digital Conversion”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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7 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

System and method for high dynamic range waveform digitization

Diverse applications from particle physics experiments to lidar are driving cost and current reduction in giga-hertz sampling rate high-resolution data conversion. Multiple imagers captures a single pixel of data and require processing at very high speed. High-bandwidth high-rate signal sampling, analog-to-digital conversion, and transfer of large amounts of data to a digital data acquisition block are required in such systems. Dynamic range, power consumption, and transfer of high-speed, high-bit width data are key implementation challenges. Data acquisition architectures optimized for specific requirements of such systems may facilitate system implementation and reduce overall system cost.

Mostafanezhad, Isar↗
DOE OSTI2024

Development of a Data Overflow Protection System for Super-Kamiokande to Maximize Data from Nearby Supernovae

Neutrinos from very nearby supernovae, such as Betelgeuse, are expected to generate more than ten million events over 10 s in Super-Kamokande (SK). At such large event rates, the buffers of the SK analog-to-digital conversion board (QBEE) will overflow, causing random loss of data that are critical for understanding the dynamics of the supernova explosion mechanism. In order to solve this problem, two new data-acquisition (DAQ) modules were developed to aid in the observation of very nearby supernovae. The first of these, the SN module, is designed to save only the number of hit photomultiplier tubes during a supernova burst and the second, the Veto module, prescales the high-rate neutrino events to prevent the QBEE from overflowing based on information from the SN module. In the event of a very nearby supernova, these modules allow SK to reconstruct the time evolution of the neutrino event rate from beginning to end using both QBEE and SN module data. This paper presents the development and testing of these modules together with an analysis of supernova-like data generated with a flashing laser diode. We demonstrate that the Veto module successfully prevents DAQ overflows for Betelgeuse-like supernovae as well as the long-term stability of the new modules. During normal running the Veto module is found to issue DAQ vetos a few times per month resulting in a total dead-time less than 1 ms, and does not influence ordinary operations. Additionally, using simulation data we find that supernovae closer than 800 pc will trigger the Veto module, resulting in a prescaling of the observed neutrino data.

F20 Instrumentation and technique↗
DOE OSTI2023

Signal Processing of Multiplexed Optical PWM Signals for Sensor Arrays in Nuclear Environments

Safe and effective generation of terrestrial nuclear power greatly benefits from the actionable data provided by the array of sensors located throughout a plant to provide a holistic online indication of reactor operation. This array includes sensors for monitoring coolant flow and pressure, temperature and heat transfer, radiation levels, structure health monitoring, and other critical parameters for reactor operation. While sensors capable of measuring these parameters have been developed, the electronics used in the pre-amplification and analog-to-digital conversion of the small signals they produce are extremely sensitive and susceptible to damage by high-temperatures and radiation environments nuclear reactors encounter while generating power. The small signals from sensors in nuclear power plants (NPPs) are transmitted over long cable runs which introduce dispersion artifacts into the signals of interest as well as electromagnetic interference (EMI) from lighting fixtures, pumps, mains electricity, and other equipment. To overcome these challenges, a front-end digitization (FREND) platform has been developed to use radiation-tolerant electronics to multiplex, amplify, and optically encode signals from an array of sensors for transmission over an optical fiber to mitigate dispersion and EMI artifacts from long runs of electrical cabling. To recover the optically transmitted data, a signal processing scheme based on 1-dimensional template matching to an indexing channel is described herein and demonstrated to have an effective bit-depth of 9.2 bits (1%). This scheme has been validated in proof-of-concept, non-nuclear testing and preliminary experimental results show good agreement between the measured optical output and and sensor input signals. The FREND system represents a low-loss data link between sensors in nuclear environments and data acquisition hardware which is aimed at improving the signal-to-noise ratio of the data acquired from these sensors to provide better information to operators and researchers.

Sweeney, Dan↗
DOE OSTI2024

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Detuned synchronized waveform averaging for reducing distortions due to sample interleaving

This invention introduces a method for optimally detuning the ratio of analog-to-digital (ADC) sample rate and trigger rate during waveform averaging to minimize the deleterious effects from sample interleaving. A prescription is described for determining the optimal detuning factor for the ADC or trigger rate in any scenario, depending on the number of ADC cores used and the limited tuning resolution of the clock rates for a specific implementation.

42 ENGINEERING↗
DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗
DOE OSTI2023

Photon-to-Digital Converters for Neutron Imaging Instruments (Final Report)

Oak Ridge National Laboratory (ORNL) collaborated with the Université de Sherbrooke (UdeS) to design a modular and scalable tile of innovative digital photodetectors called Photon-to-Digital Converters (PDC) and the required subsystems to demonstrate the feasibility of large area single-photon detectors to support high-resolution, depth-of-interaction, fast neutron radiography based on scintillation detectors. The goal is to demonstrate the advantages of using PDC over conventional Silicon Photomultiplier (SiPM) for neutron imaging systems. The basic building blocks of analog SiPM and PDC are Single-Photon Avalanche Photodiodes (SPAD). The main difference between conventional SiPMs and PDCs, is in the fact that analog SiPMs sum the charge produced by individual SPAD passively, while in PDCs each SPAD is read out individually by an active electronic circuit. Hence, PDCs provide a direct photon-to-bit conversion where a logic “1” means that there was a detection in a given SPAD. Conversely, an analog SiPM requires a sophisticated preamplifier (current amplifiers or transimpedance amplifier) followed by a shaping amplifier and an analog-to-digital converter. Moreover, since the charge from each SPAD varies slightly, the passive sum of the analog SiPM will have signal fluctuations for the same amount of photon detected. This is one of many issues that is completely eliminated by individual one-to-one SPAD read out in PDCs. The large area required for scintillator readouts for neutron imaging is such that the output capacitance of a large area of SiPM arrays is very high. This creates a burden on the signal-to-noise optimization with respect to the power budget. For PDC, the power consumption is dictated by rate of the incident photon flux, or in photon-starved environments, the dark noise rate of the SPAD array. In other words, the power consumption in the absence of events is extremely low. Hence, the power consumption of a PDC read out system is much lower than its analog counterpart. Further, the large SiPM capacitance may introduce signal distortions on the scintillator fast rise or decay time with undesired effects on timing and pulse shape discrimination. The problem is absent in PDCs, as their readout is independent on device capacitance. UdeS is the world leader in 3D vertical integration of frontside illuminated SPAD arrays over CMOS readouts. These capabilities allow future production of “3D PDC” with maximum photosensitive fill factor and electronic functionalities tailored to the application. UdeS' vast knowledge of SPADs and CMOS design made the team an ideal collaborator in the development of large area high-resolution fast neutron radiography.

42 ENGINEERING↗