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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1964

Veitch diagram plotter simplifies Boolean functions

This device for simplifying the plotting of a Veitch diagram consists of several overlays for blocking out the unwanted squares. This method of plotting the various input combinations to a computer is used in conjunction with the Boolean functions.

Rubin, D. K.↗
NASA NTRS1974

A transition calculus for Boolean functions

A transition calculus is presented for analyzing the effect of input changes on the output of logic circuits. The method is closely related to the Boolean difference, but it is more powerful. Both differentiation and integration are considered.

Tucker, J. H.↗
DOE OSTI2021

Skyrmion-Based Programmable Logic Device with Complete Boolean Logic Functions

A skyrmionic programmable logic device (SkrPLD) with complete Boolean logic functions is proposed and analyzed by micromagnetic simulations. The SkrPLD is based on an antiferromagnet/ferromagnet bilayer structure, in which the antiferromagnetic layer supports the interfacial Dzyaloshinskii–Moriya interaction and the out-of-plane exchange bias field for stabilizing a zero-field skyrmion. By varying the local exchange bias field, artificial pinning sites are introduced for trapping the skyrmions. Depending on the input currents and the initial position of skyrmions at different pinning sites, different logic functions can be realized. Micromagnetic simulations show that the proposed SkrPLD has robust performance even under thermal fluctuations and inhomogeneity effects. Our work can provide insights for the design of programmable spin logic devices.

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS1991

Depth-size tradeoffs for neural computation

The tradeoffs between the depth (i.e., the time for parallel computation) and the size (i.e., the number of threshold gates) in neural networks are studied. The authors focus the study on the neural computations of symmetric Boolean functions and some arithmetic functions. It is shown that a significant reduction in the size is possible for symmetric functions and some arithmetic functions, at the expense of a small constant increase in depth. In the process, several neural networks which have the minimum size among all the known constructions have been developed. Results on implementing symmetric functions can be used to improve results about arbitrary Boolean functions. In particular, It is shown that any Boolean function can be computed in a depth-3 neural network with O(2n/2) threshold gates; it is also proven that a minimum number of threshold gates are required.

Siu, Kai-Yeung↗
NASA NTRS2020

BDDs for Representing Data in Runtime Verification

A BDD (Boolean Decision Diagram) is a data structure for the compact representation of a Boolean function. It is equipped with efficient algorithms for minimization and for applying Boolean operators. The use of BDDs for representing Boolean functions, combined with symbolic algorithms, facilitated a leap in the capability of model checking for the verification of systems with a huge number of states. Recently BDDs were considered as an efficient representation of data for Runtime Verification (RV). We review here the basic theory of BDDs and summarize their use in model checking and specifically in runtime verification.

Peled, Doron↗
DOE OSTI2026

Testing Classical Properties from Quantum Data

Many properties of Boolean functions can be tested far more efficiently than the function itself can be learned. However, this dramatic advantage often disappears when testers are limited to random samples of ƒ instead of adaptively chosen queries to f. In this work we investigate the quantum version of this restriction: quantum algorithms that test properties of a Boolean function f solely from copies of either the function state |ƒ⟩ ∝ ∑ x |x, ƒ(x)⟩ or the phase state |(-1) ƒ ⟩ ∝ ∑ x (-1) ƒ(x) |x⟩. For monotonicity, symmetry, and triangle-freeness, we show passive quantum testers are unboundedly or super-polynomially better than their classical passive testing counterparts. They are competitive with classic query -based testers in each case. Our new testers use techniques beyond quantum Fourier sampling, and it turns out this is necessary: we show a certain class of bent functions can be tested from 𝒪(1) function states but has a sample complexity lower bound of 2 Ω(n) for any tester relying exclusively on Fourier and classical samples. Our passive quantum testers are competitive with classical query -based testers, but this isn't universal: we exhibit a testing problem that can be solved from 𝒪(1) classical queries but requires Ω(2 n/2 ) function state copies. The Forrelation problem provides a separation of the same magnitude in the opposite direction, so we conclude that quantum data and classical queries are "maximally incomparable" resources for testing. We also begin the study of lower bounds for testing from quantum data. For quantum monotonicity testing, we prove that the ensembles of [Goldreich et al., 2000; Black, 2024], which give exponential lower bounds for classical sample-based testing, do not yield any nontrivial lower bounds for testing from quantum data. New insights specific to quantum data will be required for proving copy complexity lower bounds for testing in this model.

Boolean Functions↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS1973

Theory and calculus of cubical complexes

Combination switching networks with multiple outputs may be represented by Boolean functions. Report has been prepared which describes derivation and use of extraction algorithm that may be adapted to simplification of such simultaneous Boolean functions.

Perlman, M.↗
DOE OSTI2023

Noncommutative Bohnenblust–Hille inequalities

Abstract Bohnenblust–Hille inequalities for Boolean cubes have been proven with dimension-free constants that grow subexponentially in the degree (Defant et al. in Math Ann 374(1):653–680, 2019). Such inequalities have found great applications in learning low-degree Boolean functions (Eskenazis and Ivanisvili in Proceedings of the 54th annual ACM SIGACT symposium on theory of computing, pp 203–207, 2022). Motivated by learning quantum observables, a qubit analogue of Bohnenblust–Hille inequality for Boolean cubes was recently conjectured in Rouzé et al. (Quantum Talagrand, KKL and Friedgut’s theorems and the learnability of quantum Boolean functions, 2022. arXiv preprint arXiv:2209.07279 ). The conjecture was resolved in Huang et al. (Learning to predict arbitrary quantum processes, 2022. arXiv preprint arXiv:2210.14894 ). In this paper, we give a new proof of these Bohnenblust–Hille inequalities for qubit system with constants that are dimension-free and of exponential growth in the degree. As a consequence, we obtain a junta theorem for low-degree polynomials. Using similar ideas, we also study learning problems of low degree quantum observables and Bohr’s radius phenomenon on quantum Boolean cubes.

Volberg, Alexander↗
NASA NTRS1988

Implementing neural nets with programmable logic

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Vidal, Jacques J.↗
NASA NTRS1989

Specialty functions singularity mechanics problems

The focus is in the development of more accurate and efficient advanced methods for solution of singular problems encountered in mechanics. At present, finite element methods in conjunction with special functions, boolean sum and blending interpolations are being considered. In dealing with systems which contain a singularity, special finite elements are being formulated to be used in singular regions. Further, special transition elements are being formulated to couple the special element to the mesh that models the rest of the system, and to be used in conjunction with 1-D, 2-D and 3-D elements within the same mesh. Computational simulation with a least squares fit is being utilized to construct special elements, if there is an unknown singularity in the system. A novel approach is taken in formulation of the elements in that: (1) the material properties are modified to include time, temperature, coordinate and stress dependant behavior within the element; (2) material properties vary at nodal points of the elements; (3) a hidden-symbolic computation scheme is developed and utilized in formulating the elements; and (4) special functions and boolean sum are utilized in order to interpolate the field variables and their derivatives along the boundary of the elements. It may be noted that the proposed methods are also applicable to fluids and coupled problems.

Sarigul, Nesrin↗
DOE OSTI2023

Predictor-corrector models for lightweight massive machine-type communications in Industry 4.0

Future Industry 4.0 scenarios are characterized by seamless integration between computational and physical processes. To achieve this objective, dense platforms made of small sensing nodes and other resource constraint devices are ubiquitously deployed. All these devices have a limited number of computational resources, just enough to perform the simple operation they are in charge of. The remaining operations are delegated to powerful gateways that manage sensing nodes, but resources are never unlimited, and as more and more devices are deployed on Industry 4.0 platforms, gateways present more problems to handle massive machine-type communications. Although the problems are diverse, those related to security are especially critical. To enable sensing nodes to establish secure communications, several semiconductor companies are currently promoting a new generation of devices based on Physical Unclonable Functions, whose usage grows every year in many real industrial scenarios. Those hardware devices do not consume any computational resource but force the gateway to keep large key-value catalogues for each individual node. In this context, memory usage is not scalable and processing delays increase exponentially with each new node on the platform. In this paper, we address this challenge through predictor-corrector models, representing the key-value catalogues. Models are mathematically complex, but we argue that they consume less computational resources than current approaches. The lightweight models are based on complex functions managed as Laurent series, cubic spline interpolations, and Boolean functions also developed as series. Unknown parameters in these models are predicted, and eventually corrected to calculate the output value for each given key. The initial parameters are based on the Kane Yee formula. An experimental analysis and a performance evaluation are provided in the experimental section, showing that the proposed approach causes a significant reduction in the resource consumption.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2001

Saturation: An efficient iteration strategy for symbolic state-space generation

This paper presents a novel algorithm for generating state spaces of asynchronous systems using Multi-valued Decision Diagrams. In contrast to related work, the next-state function of a system is not encoded as a single Boolean function, but as cross-products of integer functions. This permits the application of various iteration strategies to build a system's state space. In particular, this paper introduces a new elegant strategy, called saturation, and implements it in the tool SMART. On top of usually performing several orders of magnitude faster than existing BDD-based state-space generators, the algorithm's required peak memory is often close to the nal memory needed for storing the overall state spaces.

Ciardo, Gianfranco↗