Search NASA⌕ Search

SEARCH · Search NASA

Results for “C-Si”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

10 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ~ 10(exp -3). Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 +/- 2) × 10(exp -5), where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 +/- 0.6) × 10(exp -5), and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A. D↗
NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan d, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 µ m thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan d with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan d ~ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan d in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· d = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· d = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A D↗
NASA NTRS1983

Microcrystalline silicon growth for heterojunction solar cells

A total of sixteen runs of e-beam vacuum deposition of p type microcrystalline Si (m-Si) films were attempted on n type or p-n junction single crystalline Si (C-Si) substrates. The m-Si film thickness varied from .15 to .7 um and metal contacts were deposited after plasma hydrogenation. The p-m-Si on n-c-Si structure had a Voc of up to 490 m V while no Voc improvements were observed in the p-m-Si on p-n C-Si structure against p-n controls. Both CFF and Jsc were lower than control. Possible problem areas were interfaced between m-Si and C-si and the back contacts due to lack of sintering for fear of dehydrogenation.

Iles, P. A.↗
NASA NTRS1985

Hot-spot durability testing of amorphous cells and modules

This paper discusses the results of a study to determine the hot-spot susceptibility of amorphous-silicon (a-Si) cells and modules, and to provide guidelines for reducing that susceptibility. Amorphous-Si cells are shown to have hot-spot susceptibility levels similar to crystalline-silicon (C-Si) cells. This premise leads to the fact that the same general guidelines must apply to protecting a-Si cells from hot-spot stressing that apply to C-Si cells. Recommendations are made on ways of reducing a-Si module hot-spot susceptibility including the traditional method of using bypass diodes and a new method unique to thin-film cells, limiting the string current by limiting cell area.

Gonzalez, Charles↗
NASA NTRS1985

Electrochemical degradation of amorphous-silicon photovoltaic modules

Techniques of module electrochemical corrosion research, developed during reliability studies of crystalline-silicon modules (C-Si), have been applied to this new investigation into amorphous-silicon (a-Si) module reliability. Amorphous-Si cells, encapsulated in the polymers polyvinyl butyral (PVB) and ethylene vinyl acetate (EVA), were exposed for more than 1200 hours in a controlled 85 C/85 percent RH environment, with a constant 500 volts applied between the cells and an aluminum frame. Plotting power output reduction versus charge transferred reveals that about 50 percent a-Si cell failures can be expected with the passage of 0.1 to 1.0 Coulomb/cm of cell-frame edge length; this threshold is somewhat less than that determined for C-Si modules.

Mon, G. R.↗
NASA NTRS1984

Microcrystalline silicon growth for heterojunction solar cells

A single source of evaporation with B mixed with highly doped Si is used instead of the coevaporation of separate Si and B sources to reduce possible carbon contamination. The results of both the heterojunction or heteroface structures, however, are similar when evaporation is used. The best Voc of the heterojunction is about 460mV and no improvement in Voc in the heteroface structure is observed. Slight Voc degradation occurred. A study of the p m-Si/p c-Si structure showed a negative Voc in many cases. The interface properties between the two materials are such that instead of repelling minority carriers from the substrate carrier, collection actually occurred. Another study of cells made in the part of substrates not covered by n-Si results in performance lower than the controls. This indicates possible substrate degradation in the process.

Iles, P. A.↗
NASA NTRS1984

Microcrystalline silicon growth for heterojunction solar cells

Microcrystalline Si (m-Si) films with a 1.7eV energy bandgap and crystal size of several hundred A were e-beam evaporated on single crystalline Si (c-Si) to form a heterojunction with the substrate, or a window layer to a single crystalline p-n junction (heteroface structure). The goal was to enhance Voc by such uses of the larger bandgap m-Si, with the intriguing prospect of forming heterostructures with exact lattice match on each layer. The heterojunction structure was affected by interface and shunting problems and the best Voc achieved was only 482mV, well below that of single crystal Si homojunctions. The heteroface structure showed promise for some of the samples with p m-Si/p-n structure (the complementary structure did not show any improvement). Although several runs with different deposition conditions were run, the results were inconsistent. Any Voc enhancement obtained was too small to compensate for the current loss due to the extra absorption and poor carrier transport properties of the m-Si film.

Leung, D. C.↗
NASA NTRS1985

Accelerated stress testing of amorphous silicon solar cells

A technique for performing accelerated stress tests of large-area thin a-Si solar cells is presented. A computer-controlled short-interval test system employing low-cost ac-powered ELH illumination and a simulated a-Si reference cell (seven individually bandpass-filtered zero-biased crystalline PIN photodiodes) calibrated to the response of an a-Si control cell is described and illustrated with flow diagrams, drawings, and graphs. Preliminary results indicate that while most tests of a program developed for c-Si cells are applicable to a-Si cells, spurious degradation may appear in a-Si cells tested at temperatures above 130 C.

Stoddard, W. G.↗
NASA NTRS1998

Nanoscale Etching and Indentation of Silicon(001) Surface with Carbon Nanotube Tips

The possibility of nanoscale etching and indentation of Si(001)(2x1) surface by (8,0) and (10,10) carbon nanotube tips is demonstrated, for the first time, by classical molecular dynamics simulations employing Tersoff's many-body potential for a mixed C/Si/Ge system. In the nanotube tip barely touching the surface scenario atomistic etching is observed, where as in the nanoindentation scenario nanotube tip penetrates the surface without much hindrance. The results are explained in terms of the relative strength of C-C, C-Si, and Si-Si bonds.

Dzegilenko, Fendor N.↗
NASA NTRS1998

Nanoscale Etching and Indentation of Silicon Surfaces with Carbon Nanotubes

The possibility of nanolithography of silicon and germanium surfaces with bare carbon nanotube tips of scanning probe microscopy devices is considered with large scale classical molecular dynamics (MD) simulations employing Tersoff's reactive many-body potential for heteroatomic C/Si/Ge system. Lithography plays a key role in semiconductor manufacturing, and it is expected that future molecular and quantum electronic devices will be fabricated with nanolithographic and nanodeposition techniques. Carbon nanotubes, rolled up sheets of graphene made of carbon, are excellent candidates for use in nanolithography because they are extremely strong along axial direction and yet extremely elastic along radial direction. In the simulations, the interaction of a carbon nanotube tip with silicon surfaces is explored in two regimes. In the first scenario, the nanotubes barely touch the surface, while in the second they are pushed into the surface to make "nano holes". The first - gentle scenario mimics the nanotube-surface chemical reaction induced by the vertical mechanical manipulation of the nanotube. The second -digging - scenario intends to study the indentation profiles. The following results are reported in the two cases. In the first regime, depending on the surface impact site, two major outcomes outcomes are the selective removal of either a single surface atom or a surface dimer off the silicon surface. In the second regime, the indentation of a silicon substrate by the nanotube is observed. Upon the nanotube withdrawal, several surface silicon atoms are adsorbed at the tip of the nanotube causing significant rearrangements of atoms comprising the surface layer of the silicon substrate. The results are explained in terms of relative strength of C-C, C-Si, and Si-Si bonds. The proposed method is very robust and does not require applied voltage between the nanotube tips and the surface. The implications of the reported controllable etching and hole-creating for nanolithography on silicon are discussed in detail.

Dzegilenko, Fedor N.↗