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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

CMOS-Compatible Ultrathin Superconducting NbN Thin Films Deposited by Reactive Ion Sputtering on 300 mm Si Wafer

We report a milestone in achieving large-scale, ultrathin (~5 nm) superconducting NbN thin films on 300 mm Si wafers using a high-volume manufacturing (HVM) industrial physical vapor deposition (PVD) system. The NbN thin films possess remarkable structural uniformity and consistently high superconducting quality across the entire 300 mm Si wafer, by incorporating an AlN buffer layer. High-resolution X-ray diffraction and transmission electron microscopy analyses unveiled enhanced crystallinity of (111)-oriented δ-phase NbN with the AlN buffer layer. Notably, NbN films deposited on AlN-buffered Si substrates exhibited a significantly elevated superconducting critical temperature (~2 K higher for the 10 nm NbN) and a higher upper critical magnetic field or H c2 (34.06 T boost in H c2 for the 50 nm NbN) in comparison with those without AlN. These findings present a promising pathway for the integration of quantum-grade superconducting NbN films with the existing 300 mm CMOS Si platform for quantum information applications.

36 MATERIALS SCIENCE↗

Method of chemical doping that uses CMOS-compatible processes

A method of Atomic Precision Advanced Manufacturing (APAM) is provided, in which a substrate is doped from a dopant precursor gas. The method involves covering a surface of the substrate with a hard mask, selectively removing material from the hard mask such that selected areas of the substrate surface are laid bare, exposing the laid-bare areas to the dopant precursor gas, and heating the substrate so as to incorporate dopant from the dopant precursor gas into the substrate surface.

Misra, Shashank↗

Revealing the Defect‐Driven Ferroelectric Mechanisms of Aluminum Nitride

Wurtzite III-nitride compounds are CMOS-compatible with widespread industrial interest to exercise ferroelectricity, despite their polar structure being highly resistant to polarization reversal. Here, we induce and tune ferroelectric properties in w-AlN via direct-write ion-beam processing, using nanoscale patterned defect engineering as a post-growth alternative to conventional cation substitution. Nanometric piezoresponse spectroscopy of the focused He + beam patterned defect concentrations in ferroelectric Al 0.92 B 0.08 N measures a localized 10x enhancement in effective piezoresponse and 40% reduction in switching barrier. The irradiation-induced point defects convert piezoelectric AlN into a ferroelectric system with site-saturated nucleation and raise the dielectric susceptibility, switched polarization, and effective piezoelectric coefficient. Enhanced defect-lattice interactions in AlN increase carrier conduction and phonon scattering loss but preserve long-range crystallinity. Here, based on atomistic analysis of nudged elastic band density functional theory calculations and reactive force field simulations, both nitrogen vacancies and defect complexes disrupt bond ordering, facilitating a line-by-line low-barrier switching of pristine AlN.

36 MATERIALS SCIENCE↗

Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors

It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.

BEOL↗

Highly Responsive Near-Infrared Photodetector Based on Contactless PdSe 2 Integration with a Few-Layered MoSe 2 Field-Effect Transistor

Two-dimensional (2D) semiconductors with narrow bandgaps are promising candidates for near- and far-infrared (IR) photodetection, particularly in the telecommunication spectral window. However, current low-bandgap IR photodetectors face significant challenges due to their high dark current, increased carrier recombination, and thermally generated noise. Here, in this work, a hybrid phototransistor is demonstrated by integrating direct, contact-free palladium diselenide (PdSe 2 ) as a highly responsive IR detection layer with a non-IR-absorbing molybdenum diselenide (MoSe 2 ) field-effect transistor (FET), using a near-IR source at a wavelength of λ = 1650 nm. Exfoliated PdSe 2 flakes integrated into a back-gated FET architecture exhibit ambipolar transport behavior, with extracted hole and electron mobilities of 24.8 cm 2 V –1 s –1 and 58.4 cm 2 V –1 s –1 , respectively. The devices show a clear photocurrent generation under the illumination of a λ = 1650 nm laser source, achieving a notable responsivity of ∼300 mA W -1 at an applied gate voltage of 15 V, which highlights the suitability of PdSe 2 as a narrow-bandgap material for photodetection. Photoresponsivity saturates and does not have any effect above an applied gate voltage of 15 V. To further tune the photoresponsivity performance continuously with the applied gate voltage, we construct a van der Waals heterostructure phototransistor, where few layers of PdSe 2 are directly transferred onto the 2D channel region of a MoSe 2 FET, while avoiding any contact with the metal electrodes. In this heterostructure, PdSe 2 works as the primary active IR-absorbing layer, while MoSe 2 provides high-performance FET characteristics. This spatial separation of absorption and transport facilitates efficient interlayer charge transfer and charge separation, resulting in high responsivities of up to 972 mA W –1 at near-IR wavelengths and a low power density of 1.5 mW/mm 2 . The responsivity of our photodetector is comparable to that of some state-of-the-art commercially available NIR photodetectors, highlighting the potential of PdSe 2 -based heterostructures as scalable, CMOS-compatible platforms for high-performance near-IR detection.

Infrared (IR) photodetectors↗

Patterned, Low-Temperature Growth of Transition Metal Dichalcogenides for Low Resistance Raised Contacts

Transition metal dichalcogenide (TMD) monolayers are promising channel materials for next-generation electronic devices. A challenge is the high contact resistance between monolayer TMDs and metal contacts, especially for holes. Here, in this regard, raised source/drain contacts are promising. However, the direct, patterned growth of raised contacts at CMOS-compatible temperatures remains largely unresolved. We present plasma-free selenization and sulfurization of metal oxides at substrate temperatures down to 400 °C, compatible with back-end-of-line thermal budgets. To achieve growth at such temperatures, gas-phase chalcogen precursors are first thermally activated at 950 °C. Films grown on single-crystal monolayer TMDs exhibit high crystal quality, as confirmed by transmission electron microscopy. Raised contacts on WSe 2 monolayers fabricated using this approach yield a low hole contact resistance of 0.3 kΩ·μm after chemical doping. This process is shown to be applicable to growing various TMDs, including WS 2 , MoSe 2 , MoS 2 , PtSe 2 , and NbS 2 .

contact engineering↗

Heteroepitaxial control of thickness, strain, and domain architecture in few-layer ferroelectric tin monochalcogenides

Thin-film epitaxy and epitaxial strain have been widely exploited to tune domain configurations, switching behavior, and ferroic properties in conventional three-dimensional ferroelectric thin films; however, its application to controlling the properties of two-dimensional (2D) ferroelectrics has remained largely unexplored. Here, using SnX (X = Se, S) as a model system, we demonstrate heteroepitaxial control of thickness, strain state, and domain architecture in few-layer ferroelectric SnX via growth on monolayer MoS2 van der Waals (vdW) templates. Compared with conventional growth, MoS2-templated heteroepitaxy promotes epitaxial alignment, yielding ultrathin SnSe films with improved crystalline quality, full areal coverage, and enlarged lateral dimensions. Strong interfacial epitaxial coupling induces pronounced in-plane strain and stabilizes a hierarchical ferroelastic domain architecture, in which long-range 90° stripe domains are further subdivided into nanoscale rotational variants, as revealed by scanning transmission electron microscopy and synchrotron X-ray microscopy. Piezoresponse force microscopy and second-harmonic polarimetry confirm robust in-plane polarization, while ferroelectricity in SnSe is established through polarization-electric field hysteresis and nonvolatile ferroelectric resistive switching with on/off ratios approaching 1000. A nonvolatile, switchable ferroelectric diode effect further evidences direct coupling between polarization and charge transport. Notably, ferroelectric switchability exhibits a strong thickness dependence and is preserved only below ∼10 layers. This vdW heteroepitaxial strategy is further extended to ferroelectric SnS. The seamless heteroepitaxial integration of 2D ferroelectrics with CMOS-compatible, wafer-scale MoS2 templates provides a general and scalable route for strain-enabled structural and ferroelectric engineering in emerging memory and low-power optoelectronic applications.

Wang, Yueyin↗

Slow-Light Mid-IR Silicon Photonic Chips for NO 2 and CH 4 Gas Detection

A compact, chip-scale mid-infrared gas sensor is demonstrated, leveraging a two-dimensional photonic crystal waveguide (PCW) fabricated on a silicon-on-insulator (SOI) platform. The PCW comprises a hexagonal lattice with lattice constant a = 860 nm and hole radius r = 0.22a, incorporating a central line defect of reduced-radius holes (r s = 0.7r) to induce slow-light propagation near the photonic band edge with a group index of approximately 73, thereby enhancing light-matter interaction. The sensor operates at fundamental absorption wavelengths of 3.42 μm for nitrogen dioxide (NO 2 ) and 3.40 μm for methane (CH 4 ), utilizing the strongest molecular vibrational transitions for maximum sensitivity. Experimental validation was conducted using dynamically diluted gas mixtures generated by mass flow controllers, with signal acquisition performed by a liquid nitrogen-cooled InSb detector. For NO 2 , the sensor exhibited excellent linear response over 5–25 ppm (part per million) with coefficient of determination R 2 = 0.9934, achieving a detection limit of 210 ppb (part per billion)─representing the first reported silicon photonic-based NO 2 detection. For CH 4 , exposure to 25 ppm resulted in a 6.4% decrease in transmitted intensity, demonstrating multigas sensing capability. The CMOS-compatible fabrication process and compact 3 mm device footprint establish this SOI-PCW platform as a scalable, low-power solution for integrated mid-infrared gas sensing, with significant potential for environmental monitoring and industrial safety applications.

Crystals↗

Silicon-On-Sapphire Metasurfaces Generate Arrays of Dark and Bright Traps for Neutral Atoms

We demonstrated crystalline silicon-on-sapphire (c-SOS) metasurfaces that convert a Gaussian beam into arrays of complex optical traps, including arrays of optical bottle beams that trap atoms in dark regions interleaved with bright tweezer arrays. The high refractive index and indirect band gap of crystalline silicon make it possible to design high-resolution near-infrared (λ > 700 nm) metasurfaces that can be manufactured at scale using CMOS-compatible processes. Compared with active components like spatial light modulators (SLMs) that have become widely used to generate trap arrays, metasurfaces provide an indefinitely scalable number of pixels, enabling large arrays of complex traps in a very small form factor, as well as reduced dynamic noise. To design metasurfaces that can generate three-dimensional bottle beams to serve as dark traps, we modified the Gerchberg-Saxton algorithm to enforce complex-amplitude profiles at the focal plane of the metasurface and to optimize the uniformity of the traps across the array. We fabricated and measured c-SOS metasurfaces that convert a Gaussian laser beam into arrays of bright traps, dark traps, and interleaved bright/dark traps.

Gerchberg-Saxton↗

Piezoelectrically actuated silicon-nitride-based high-speed spatial light modulator

Advancements in light modulator technology have been driving discoveries and progress across various fields. The problem of large-scale coherent optical control of atomic quantum systems—including cold atoms, ions, and solid-state color centers—presents among the most stringent requirements. This motivates a new generation of high-speed large-scale modulator technology operating in the visible to near-infrared wavelength range. We introduce a scalable modulator technology based on piezoelectrically actuated silicon nitride resonant waveguide gratings fabricated on 200 mm diameter silicon wafers with CMOS-compatible processes. We present a proof-of-concept device with 4 × 4 individually addressable 50 μ m × 50 μ m pixels or channels, each containing a resonant waveguide grating with a ~ 780 nm design wavelength, supporting > 100 MHz modulation speeds, and a spectral response with > 20 dB extinction.

integrated optics↗

Protonic nickelate device networks for spatiotemporal neuromorphic computing

Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging, as most neuromorphic devices emulate only isolated neuron- or synapse-like functions. Here we introduce an integrated neuromorphic computing platform in which both nonlinear spatiotemporal processing and programmable memory are realized within a single perovskite nickelate material system. By engineering symmetric and asymmetric hydrogenated NdNiO 3 junction devices on the same wafer, we combine ultrafast, proton-mediated transient dynamics with stable multilevel resistance states. Networks of symmetric NdNiO 3 junctions exhibit emergent spatial interactions mediated by proton redistribution, while each node simultaneously provides short-term temporal memory, enabling nanosecond-scale operation with an energy cost of ~0.2 nJ per input. When interfaced with asymmetric output units serving as reconfigurable long-term weights, these networks allow both feature transformation and linear classification in the same material system. Leveraging these emergent interactions, the platform enables real-time pattern recognition and achieves high accuracy in spoken digit classification and early seizure detection, outperforming temporal-only or uncoupled architectures. These results position protonic nickelates as a compact, energy-efficient, CMOS-compatible platform that integrates processing and memory for scalable intelligent hardware.

Electrical and electronic engineering↗

Bottom-up fabrication of 2D Rydberg exciton arrays in cuprous oxide

Solid-state platforms provide exceptional opportunities for advancing on-chip quantum technologies by enhancing interaction strengths through coupling, scalability, and robustness. Cuprous oxide (Cu 2 O) has recently emerged as a promising medium for scalable quantum technology due to its high-lying Rydberg excitonic states, akin to those in hydrogen atoms. To harness these nonlinearities for quantum applications, the confinement dimensions must match the Rydberg blockade size, which can reach several microns in Cu 2 O. Using a CMOS-compatible growth technique, this study demonstrates the bottom-up fabrication of site-selective arrays of Cu 2 O microparticles. We observed Rydberg excitons up to the principal quantum number n = 5 within these Cu 2 O arrays on a quartz substrate and analyzed the spatial variation of their spectrum across the array, showing robustness and reproducibility on a large chip. These results lay the groundwork for the deterministic growth of Cu 2 O around photonic structures, enabling substantial light-matter interaction on integrated photonic platforms and paving the way for scalable, on-chip quantum devices.

36 MATERIALS SCIENCE↗

Thermally generated magnonic spin currents in a polycrystalline gadolinium iron garnet thin film with perpendicular magnetic anisotropy

Rare-earth iron garnets (REIGs) are the benchmark systems for magnonics, including the longitudinal spin Seebeck effect (LSSE). While most research has focused on single-crystalline REIGs on complimentary garnet substrates, moving to more, cost-effective complementary metal-oxide semiconductor (CMOS)-compatible substrates is important to integrate REIG thin films with existing technology. In this regard, we grow a 130 nm-thick polycrystalline gadolinium iron garnet (GdIG) film on the Si/SiO2 substrate and investigate the temperature-dependent LSSE. Interestingly, the polycrystalline GdIG film exhibits perpendicular magnetic anisotropy (PMA) at room temperature which is induced by tensile in-plane (IP)-strain originating from the thermal-expansion mismatch between the GdIG film and the substrate during rapid thermal annealing. Further, a spin-reorientation transition from the out-of-plane IP direction below TS = 180 K is observed. Additionally, the film reveals a magnetic compensation temperature, TComp, of ≈240 K. The LSSE voltage not only demonstrates a sign-inversion around TComp, but also shows noticeable changes around TS. As compared to a single-crystalline GdIG film, the lower LSSE voltage for the polycrystalline GdIG is attributed to the higher effective magnetic anisotropy and enhanced magnon scattering at the grain boundaries. Our study not only paves the way for the cost-effective growth of CMOS-compatible REIG-based systems with PMA for magnonic memory and information processing applications, but also highlights the fact that the spincaloritronic and spin-insulatronic properties of the polycrystalline REIGs follow those of their single-crystalline counterparts with reduced spin-to-charge conversion efficiency through LSSE which can be tuned further by controlling the average gran size and interface engineering.

Physics↗

Isolation of individual Er quantum emitters in anatase TiO 2 on Si photonics

Defects and dopant atoms in solid state materials are a promising platform for realizing single photon sources and quantum memories, which are the basic building blocks of quantum repeaters needed for long distance quantum networks. In particular, trivalent erbium (Er 3+ ) is of interest because it couples C-band telecom optical transitions with a spin-based memory platform. In order to produce quantum repeaters at the scale required for quantum networks it is imperative to integrate these necessary building blocks with mature and scalable semiconductor processes. Here, in this work, we demonstrate the optical isolation of single Er 3+ ions in CMOS-compatible titanium dioxide (TiO 2 ) thin films monolithically integrated on a silicon-on-insulator photonics platform. Our results demonstrate an initial step toward the realization of a monolithically integrated and scalable quantum photonics package based on Er 3+ doped thin films.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

CMOS-Based Single-Cycle in-Memory XOR/XNOR

Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification. XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms. The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations. Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations. The existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process. Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2× improvement in the latency compared with other existing CMOS-compatible solutions. We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.

97 MATHEMATICS AND COMPUTING↗

DS-GL: Advancing Graph Learning via Harnessing the Power of Nature within Dynamic Systems

With the rapid digitization of the world, an increasing number of real-world applications are turning to nonEuclidean data, modeled as graphs. Due to their intrinsic high complexity and irregularity, learning from graph data demands tremendous computational power. Recently, CMOS-compatible Ising machines, i.e., dynamic systems composed of CMOS components, have emerged as a new approach that harnesses the inherent power of natural annealing within dynamic systems to efficiently resolve binary optimization problems and have been adopted for traditional graph computation, such as max-cut. However, when performing complex Graph Learning (GL) tasks, Ising machines face significant hurdles: (i) they are inherently binary and thus ill-suited for real-valued problems; (ii) their expensive all-to-all coupling network that guarantees effective natural annealing poses daunting scalability concerns. To address these challenges, this paper proposes a nature-powered graph learning framework dubbed DS-GL, which is the first effort to transform the process of solving graph learning problems into the natural annealing process within a parameterized dynamic system embodied as a CMOS chip. To tackle the two major hurdles, DS-GL first augments the Ising machine architecture to modify the self-reaction term of its Hamiltonian function from linear to quadratic, effectively serving as an energy regulator. This adjustment maintains the system’s original physical interpretation while enabling it to process continuous, real-valued data. Second, to address the scaling issue, DS-GL further upgrades the real-valued dense Ising machine by decomposing it into a mesh-based multi-PE dynamic system that supports efficient distributed spatial-temporal co-annealing across different PEs through sparse interconnects. By exploiting the inherent sparsity and component structures in real-world graphs, DS-GL is able to map complex graph learning tasks onto the scalable dynamic system while maintaining high accuracy. Evaluations with three diverse GL applications across six real-world datasets, including traffic flow and COVID-19 prediction, show that DS-GL can deliver from 102× to 106× speedups and 500× energy reduction over Graph Neural Networks on GPUs, with 5% - 20% accuracy enhancement.

Song, Ruibing↗

Amorphous boron nitride: synthesis, properties and device application

Amorphous boron nitride (a-BN) exhibits remarkable electrical, optical, and chemical properties, alongside robust mechanical stability, making it a compelling material for advanced applications in nanoelectronics and photonics. This review comprehensively examines the unique characteristics of a-BN, emphasizing its electrical and optical attributes, state-of-the-art synthesis techniques, and device applications. Key advancements in low-temperature growth methods for a-BN are highlighted, offering insights into their potential for integration into scalable, CMOS-compatible platforms. Additionally, the review discusses the emerging role of a-BN as a dielectric material in electronic and photonic devices, serving as substrates, encapsulation layers, and gate insulators. Finally, perspectives on future challenges, including defect control, interface engineering, and scalability, are presented, providing a roadmap for realizing the full potential of a-BN in next-generation device technologies.

36 MATERIALS SCIENCE↗

Direct electron beam patterning of electro-optically active PEDOT:PSS

The optical and electronic tunability of the conductive polymer poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) has enabled emerging applications as diverse as bioelectronics, flexible electronics, and micro- and nano-photonics. High-resolution spatial patterning of PEDOT:PSS opens up opportunities for novel active devices in a range of fields. However, typical lithographic processes require tedious indirect patterning and dry etch processes, while solution-processing methods such as ink-jet printing have limited spatial resolution. Here, we report a method for direct write nano-patterning of commercially available PEDOT:PSS through electron-beam induced solubility modulation. The written structures are water stable and maintain the conductivity as well as electrochemical and optical properties of PEDOT:PSS, highlighting the broad utility of our method. We demonstrate the potential of our strategy by preparing prototypical nano-wire structures with feature sizes down to 250 nm, an order of magnitude finer than previously reported direct write methods, opening the possibility of writing chip-scale microelectronic and optical devices. We finally use the high-resolution writing capabilities to fabricate electrically-switchable optical diffraction gratings. We show active switching in this archetypal system with >95 % contrast at CMOS-compatible voltages of +2 V and -3 V, offering a route towards highly-miniaturized dynamic optoelectronic devices.

42 ENGINEERING↗