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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Analytical Expression for DC Link Capacitor Current in a Cascaded H-Bridge Multi-Level Active Front-End Converter

Medium-voltage grid-tied systems often use a cascaded H-bridge multi-level active front-end. In this converter, dc link bus capacitors play an important role in stabilizing the converter and enabling both active and reactive power injections. The present work provides analytical expressions for the capacitor current, which are essential for optimizing system design (especially capacitor size vs. lifetime). Then, the expression is incorporated into the grid connected bidirectional power system model. Consequently, this work contributes to the guiding principles to choose accurate dc link capacitor ratings against grid-side power delivery requirements. The analytical results have been validated with detailed simulations and hardware results.

cascaded H-bridge, carrier-based PWM, dc-link capa↗
DOE OSTI2020

Transient pulse‐based impedance characterisation of DC‐link capacitor for EV systems

In this study, a method for impedance characterisation of DC‐link capacitors based on transient pulse analysis is proposed. The fundamentals of the concept are presented and design considerations are discussed. The functionality of the proposed approach is supported by SPICE simulation with two different commercial capacitors from different manufacturers and validated with experimental results. Experimental results for equivalent series resistance, equivalent series inductance (ESL) and capacitance estimation are presented for commercial DC‐link capacitors and compared with component analyser results. The simulation and experimental results show that the proposed method is a promising candidate for capacitance and ESL estimation of capacitors in EV traction systems.

Gurpinar, Emre↗
NASA NTRS2011

Capacitor Test, Evaluation. and Modeling Within NASA Electronic Parts and Packaging (NEPP) Program. "Why Ceramic Capacitors Fracture During Manual Soldering and How to Avoid Failures"

Presentation discusses: (1) Why Multi-Layer Ceramic Capacitors(MLCCs) crack during manual soldering? Workmanship and parts issues. (2) Do existing qualification requirements assure crack-free soldering? MIL-spec Thermal Shock (TS) testing. MIL-spec Resistance to Soldering Heat (RSH) test. (3) What test can assure reliable soldering? Mechanical characteristics of ceramics. Comparison of three TS techniques: LND, TSD, and IWT. (4) Simulation of TS conditions.

Teverovsky, Alexander↗
NASA NTRS2010

Physical and Electrical Characterization of Aluminum Polymer Capacitors

Conductive polymer aluminum capacitor (PA capacitor) is an evolution of traditional wet electrolyte aluminum capacitors by replacing liquid electrolyte with a solid, highly conductive polymer. On the other hand, the cathode construction in polymer aluminum capacitors with coating of carbon and silver epoxy for terminal connection is more like a combination of the technique that solid tantalum capacitor utilizes. This evolution and combination result in the development of several competing capacitor construction technologies in manufacturing polymer aluminum capacitors. The driving force of this research on characterization of polymer aluminum capacitors is the rapid progress in IC technology. With the microprocessor speeds exceeding a gigahertz and CPU current demands of 80 amps and more, the demand for capacitors with higher peak current and faster repetition rates bring conducting polymer capacitors to the center o( focus. This is because this type of capacitors has been known for its ultra-low ESR and high capacitance. Polymer aluminum capacitors from several manufacturers with various combinations of capacitance, rated voltage, and ESR values were obtained and tested. The construction analysis of the capacitors revealed three different constructions: conventional rolled foil, the multilayer stacking V-shape, and a dual-layer sandwich structure. The capacitor structure and its impact on the electrical characteristics has been revealed and evaluated. A destructive test with massive current over stress to fail the polymer aluminum capacitors reveals that all polymer aluminum capacitors failed in a benign mode without ignition, combustion, or any other catastrophic failures. The extraordinary low ESR (as low as 3 mOMEGA), superior frequency independence reported for polymer aluminum capacitors have been confirmed. For the applications of polymer aluminum capacitors in space programs, a thermal vacuum cycle test was performed. The results, as expected, show no impact on the electrical characteristics of the capacitors. The breakdown voltage of polymer capacitors has been evaluated using a steady step surge test. Initial results show the uniform distribution in the breakdown voltage for polymer aluminum capacitors. Polymer aluminum capacitors with a combination of very high capacitance, extraordinary low ESR, excellent frequency stability, and non-ignite benign failure mode make it a niche fit in space applications for both today and future. Polymer capacitors are apparently also the best substitutes of the currently used MnO2-based tantalum capacitors in the low voltage range. However, some critical aspects are still to be addressed in the next phase of the investigation for PA capacitors. These include the long term reliability test of 125 C dry life and 85 C/85%RH humidity, the failure mechanism and de-rating, the radiation tolerance, and the high temperature performance. All of the above requires the continuous NEPP funding and support.

Liu, David (Donghang)↗
NASA NTRS2011

Reliability Evaluation of Base-Metal-Electrode Multilayer Ceramic Capacitors for Potential Space Applications

Base-metal-electrode (BME) ceramic capacitors are being investigated for possible use in high-reliability spacelevel applications. This paper focuses on how BME capacitors construction and microstructure affects their lifetime and reliability. Examination of the construction and microstructure of commercial off-the-shelf (COTS) BME capacitors reveals great variance in dielectric layer thickness, even among BME capacitors with the same rated voltage. Compared to PME (precious-metal-electrode) capacitors, BME capacitors exhibit a denser and more uniform microstructure, with an average grain size between 0.3 and 0.5 m, which is much less than that of most PME capacitors. BME capacitors can be fabricated with more internal electrode layers and thinner dielectric layers than PME capacitors because they have a fine-grained microstructure and do not shrink much during ceramic sintering. This makes it possible for BME capacitors to achieve a very high capacitance volumetric efficiency. The reliability of BME and PME capacitors was investigated using highly accelerated life testing (HALT). Most BME capacitors were found to fail with an early avalanche breakdown, followed by a regular dielectric wearout failure during the HALT test. When most of the early failures, characterized with avalanche breakdown, were removed, BME capacitors exhibited a minimum mean time-to-failure (MTTF) of more than 105 years at room temperature and rated voltage. Dielectric thickness was found to be a critical parameter for the reliability of BME capacitors. The number of stacked grains in a dielectric layer appears to play a significant role in determining BME capacitor reliability. Although dielectric layer thickness varies for a given rated voltage in BME capacitors, the number of stacked grains is relatively consistent, typically around 12 for a number of BME capacitors with a rated voltage of 25V. This may suggest that the number of grains per dielectric layer is more critical than the thickness itself for determining the rated voltage and the life expectancy of the BME capacitor. The leakage current characterization and the failure analysis results suggest that most of these early avalanche failures are due to the extrinsic minor construction defects introduced during fabrication of BME capacitors. The concentration of the extrinsic defects must be reduced if the BME capacitors are considered for high reliability applications. There are two approaches that can reduce or prevent the occurrence of early failure in BME capacitors: (1) to reduce the defect concentration with improved processing control; (2) to prevent the use of BME capacitors under harsh external stress levels so that the extrinsic defects will never be triggered for a failure. In order to do so appropriate dielectric layer thickness must be determined for a given rated voltage.

Liu, David (Donhang)↗
NASA NTRS2011

Reliability Evaluation of Base-Metal-Electrode (BME) Multilayer Ceramic Capacitors for Space Applications

This paper reports reliability evaluation of BME ceramic capacitors for possible high reliability space-level applications. The study is focused on the construction and microstructure of BME capacitors and their impacts on the capacitor life reliability. First, the examinations of the construction and microstructure of commercial-off-the-shelf (COTS) BME capacitors show great variance in dielectric layer thickness, even among BME capacitors with the same rated voltage. Compared to PME (precious-metal-electrode) capacitors, BME capacitors exhibit a denser and more uniform microstructure, with an average grain size between 0.3 and approximately 0.5 micrometers, which is much less than that of most PME capacitors. The primary reasons that a BME capacitor can be fabricated with more internal electrode layers and less dielectric layer thickness is that it has a fine-grained microstructure and does not shrink much during ceramic sintering. This results in the BME capacitors a very high volumetric efficiency. The reliability of BME and PME capacitors was investigated using highly accelerated life testing (HALT) and regular life testing as per MIL-PRF-123. Most BME capacitors were found to fail· with an early dielectric wearout, followed by a rapid wearout failure mode during the HALT test. When most of the early wearout failures were removed, BME capacitors exhibited a minimum mean time-to-failure of more than 10(exp 5) years. Dielectric thickness was found to be a critical parameter for the reliability of BME capacitors. The number of stacked grains in a dielectric layer appears to play a significant role in determining BME capacitor reliability. Although dielectric layer thickness varies for a given rated voltage in BME capacitors, the number of stacked grains is relatively consistent, typically between 10 and 20. This may suggest that the number of grains per dielectric layer is more critical than the thickness itself for determining the rated voltage and the life expectancy of the BME capacitor. Since BME capacitors have a much smaller grain size than PME capacitors, it is reasonable to predict that BME capacitors with thinner dielectric layers may have an equivalent life expectancy to that of PME capacitors with thicker dielectric layers.

Liu, David (Donghang)↗
NASA NTRS2011

Failure Modes in Capacitors When Tested Under a Time-Varying Stress

Power-on failure has been the prevalent failure mechanism for solid tantalum capacitors in decoupling applications. A surge step stress test (SSST) has been previously applied to identify the critical stress level of a capacitor batch to give some predictability to the power-on failure mechanism [1]. But SSST can also be viewed as an electrically destructive test under a time-varying stress (voltage). It consists of rapidly charging the capacitor with incremental voltage increases, through a low resistance in series, until the capacitor under test is electrically shorted. When the reliability of capacitors is evaluated, a highly accelerated life test (HALT) is usually adopted since it is a time-efficient method of determining the failure mechanism; however, a destructive test under a time-varying stress such as SSST is even more time efficient. It usually takes days or weeks to complete a HALT test, but it only takes minutes for a time-varying stress test to produce failures. The advantage of incorporating a specific time-varying stress profile into a statistical model is significant in providing an alternative life test method for quickly revealing the failure mechanism in capacitors. In this paper, a time-varying stress that mimics a typical SSST has been incorporated into the Weibull model to characterize the failure mechanism in different types of capacitors. The SSST circuit and transient conditions for correctly surge testing capacitors are discussed. Finally, the SSST was applied for testing Ta capacitors, polymer aluminum capacitors (PA capacitors), and multi-layer ceramic (MLC) capacitors with both precious metal electrodes (PME) and base metal electrodes (BME). The test results are found to be directly associated with the dielectric layer breakdown in Ta and PA capacitors and are independent of the capacitor values, the way the capacitors were built, and the capacitors manufacturers. The test results also show that MLC capacitors exhibit surge breakdown voltages much higher than the rated voltage and that the breakdown field is inversely proportional to the dielectric layer thickness. The SSST data can also be used to comparatively evaluate the voltage robustness of capacitors for decoupling applications.

Liu, David (Donhang)↗
NASA NTRS2003

Capacitor-Chain Successive-Approximation ADC

A proposed successive-approximation analog-to-digital converter (ADC) would contain a capacitively terminated chain of identical capacitor cells. Like a conventional successive-approximation ADC containing a bank of binary-scaled capacitors, the proposed ADC would store an input voltage on a sample-and-hold capacitor and would digitize the stored input voltage by finding the closest match between this voltage and a capacitively generated sum of binary fractions of a reference voltage (Vref). However, the proposed capacitor-chain ADC would offer two major advantages over a conventional binary-scaled-capacitor ADC: (1) In a conventional ADC that digitizes to n bits, the largest capacitor (representing the most significant bit) must have 2(exp n-1) times as much capacitance, and hence, approximately 2(exp n-1) times as much area as does the smallest capacitor (representing the least significant bit), so that the total capacitor area must be 2(exp n) times that of the smallest capacitor. In the proposed capacitor-chain ADC, there would be three capacitors per cell, each approximately equal to the smallest capacitor in the conventional ADC, and there would be one cell per bit. Therefore, the total capacitor area would be only about 3(exp n) times that of the smallest capacitor. The net result would be that the proposed ADC could be considerably smaller than the conventional ADC. (2) Because of edge effects, parasitic capacitances, and manufacturing tolerances, it is difficult to make capacitor banks in which the values of capacitance are scaled by powers of 2 to the required precision. In contrast, because all the capacitors in the proposed ADC would be identical, the problem of precise binary scaling would not arise.

Cunningham, Thomas↗
NASA NTRS2011

Failure Modes in Capacitors When Tested Under a Time-Varying Stress

Steady step surge testing (SSST) is widely applied to screen out potential power-on failures in solid tantalum capacitors. The test simulates the power supply's on and off characteristics. Power-on failure has been the prevalent failure mechanism for solid tantalum capacitors for decoupling applications. On the other hand, the SSST can also be reviewed as an electrically destructive test under a time-varying stress. It consists of rapidly charging the capacitor with incremental voltage increases, through a low resistance in series, until the capacitor under test is electrically shorted. Highly accelerated life testing (HALT) is usually a time-efficient method for determining the failure mechanism in capacitors; however, a destructive test under a time-varying stress like SSST is even more effective. It normally takes days to complete a HALT test, but it only takes minutes for a time-varying stress test to produce failures. The advantage of incorporating specific time-varying stress into a statistical model is significant in providing an alternative life test method for quickly revealing the failure modes in capacitors. In this paper, a time-varying stress has been incorporated into the Weibull model to characterize the failure modes. The SSST circuit and transient conditions to correctly test the capacitors is discussed. Finally, the SSST was applied for testing polymer aluminum capacitors (PA capacitors), Ta capacitors, and multi-layer ceramic capacitors with both precious metal electrode (PME) and base-metal-electrodes (BME). It appears that testing results are directly associated to the dielectric layer breakdown in PA and Ta capacitors and are independent on the capacitor values, the way the capacitors being built, and the manufactures. The testing results also reveal that ceramic capacitors exhibit breakdown voltages more than 20 times the rated voltage, and the breakdown voltages are inverse proportional to the dielectric layer thickness. The possibility of ceramic capacitors in front-end decoupling applications to block the surge noise from a power supply is also discussed.

Liu, David (Donhang)↗
NASA NTRS2009

Electrically Variable or Programmable Nonvolatile Capacitors

Electrically variable or programmable capacitors based on the unique properties of thin perovskite films are undergoing development. These capacitors show promise of overcoming two important deficiencies of prior electrically programmable capacitors: Unlike in the case of varactors, it is not necessary to supply power continuously to make these capacitors retain their capacitance values. Hence, these capacitors may prove useful as components of nonvolatile analog and digital electronic memories. Unlike in the case of ferroelectric capacitors, it is possible to measure the capacitance values of these capacitors without changing the values. In other words, whereas readout of ferroelectric capacitors is destructive, readout of these capacitors can be nondestructive. A capacitor of this type is a simple two terminal device. It includes a thin film of a suitable perovskite as the dielectric layer, sandwiched between two metal or metal oxide electrodes (for example, see Figure 1). The utility of this device as a variable capacitor is based on a phenomenon, known as electrical-pulse-induced capacitance (EPIC), that is observed in thin perovskite films and especially in those thin perovskite films that exhibit the colossal magnetoresistive (CMR) effect. In EPIC, the application of one or more electrical pulses that exceed a threshold magnitude (typically somewhat less than 1 V) gives rise to a nonvolatile change in capacitance. The change in capacitance depends on the magnitude duration, polarity, and number of pulses. It is not necessary to apply a magnetic field or to cool the device below (or heat it above) room temperature to obtain EPIC. Examples of suitable CMR perovskites include Pr(1-x)Ca(x)MnO3, La(1-x)S-r(x)MnO3,and Nb(1-x)Ca(x)MnO3. Figure 2 is a block diagram showing an EPIC capacitor connected to a circuit that can vary the capacitance, measure the capacitance, and/or measure the resistance of the capacitor.

Shangqing, Liu↗