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DOE OSTI2022

System-on-chip integrated circuit technology applications on the DIII-D tokamak for multi-field measurements

Several mm-wave diagnostics on the DIII-D tokamak provide multi-scale and multi-dimensional measurements of plasma profile evolution and turbulence fluctuations. Mm-wave fusion plasma diagnostics that adopt system-on-chip integrated circuit technology can provide better space utilization, flexible installation, and improved sensitivity. In order to further extend this technology for additional fusion facilities with a higher toroidal magnetic field, V-band (55–75 GHz) and F-band (90–140 GHz) chips for Microwave Imaging Reflectometer (MIR) and Electron Cyclotron Emission Imaging (ECEI) instruments are developed and tested in the Davis Millimeter Wave Research Center (DMRC). Current measurement data show that correlation between these SoC-based diagnostic instruments with other state-of-the-art diagnostics enables co-located multi-field turbulence fluctuation measurement.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

DOE OSTI2022

The Simulation and Design of an On-Chip Superconducting Millimetre Filter-Bank Spectrometer

Abstract Superconducting on-chip filter banks provide a scalable, space saving solution to create imaging spectrometers at millimetre and submillimetre wavelengths. We present an easy to realise, lithographed superconducting filter design with a high tolerance to fabrication error. Using a capacitively coupled $$\lambda /2$$ λ / 2 microstrip resonator to define a narrow ( $$\lambda /\Delta \lambda = 300$$ λ / Δ λ = 300 ) spectral pass band, the filtered output of a given spectrometer channel directly connects to a lumped-element kinetic inductance detector. We show the tolerance analysis of our design, demonstrating $$<11\%$$ < 11 % change in filter quality factor to any one realistic fabrication error and a full filter-bank efficiency forecast to be 50% after accounting for fabrication errors and dielectric loss tangent.

Robson, G. (ORCID:0000000315279326)↗

NASA NTRS2019

Integrated Circuit (IC) Chip with a Self-Contained Fluid Sensor and Method of Making the Chip

An integrated circuit (IC) chip with a self-contained fluid sensor and method of making the chip. The sensor is in a conduit formed between a semiconductor substrate and a non-conductive cap with fluid entry and exit points through the cap. The conduit may be entirely in the cap, in the substrate or in both. The conduit includes encased temperature sensors at both ends and a central encased heater. The temperature sensors may each include multiple encased diodes and the heater may include multiple encased resistors.

Manos, George↗

NASA NTRS1975

A 1-1/2-level on-chip-decoding bubble memory chip design

Design includes multi-channel replicator which can reduce chip-writing requirement, selective annihilating switch which can effectively annihilate bubbles with minimum delay, and modified transfer switch which can be used as selective steering-type decoder.

Chen, T. T.↗

DOE OSTI2020

China’s Bid To Lead Artificial Intelligence Chip Development within the Decade

In 2017, the Chinese government announced an ambitious, broad strategy to become the global leader in artificial intelligence (AI) theories, technologies, and applications by 2030 and indicated that China’s ability to indigenously produce cutting-edge AI chips would be integral to its success. China’s goal to become a dominant producer of AI hardware within a decade is a bold undertaking because China faces domestic chip production challenges and fierce competition from US chip producers. Our review of Chinese AI chip product lines shows various levels where Chinese companies compete with global firms in the production chain. China lacks a robust indigenous AI chip production infrastructure, and the United States and its allies are tightening controls on the supply of advanced semiconductor manufacturing equipment (SME) and electronic design automation (EDA) software to China. In contrast to their Chinese counterparts, US companies operate in all areas of AI chip production and have consistently driven the development of new chip designs. AI chip production is a costly endeavor, and China’s chip producers currently lack the customer base to lead global AI chip development by the 2030 goal. An expanded customer base may help China attract the necessary expertise to bolster its AI chip production chain. This would also help Chinese producers make their investments in the requisite technology economically sustainable. Chinese researchers continue to pursue promising next-generation AI chip designs, such as neuromorphic computing-based architectures, which in the next five to ten years could position Chinese companies to make or contribute to key innovations in the field.

74 ATOMIC AND MOLECULAR PHYSICS↗

NASA NTRS2011

Cytometer on a Chip

A cytometer now under development exploits spatial sorting of sampled cells on a microarray chip followed by use of grating-coupled surface-plasmon-resonance imaging (GCSPRI) to detect the sorted cells. This cytometer on a chip is a prototype of contemplated future miniature cytometers that would be suitable for rapidly identifying pathogens and other cells of interest in both field and laboratory applications and that would be attractive as alternatives to conventional flow cytometers. The basic principle of operation of a conventional flow cytometer requires fluorescent labeling of sampled cells, stringent optical alignment of a laser beam with a narrow orifice, and flow of the cells through the orifice, which is subject to clogging. In contrast, the principle of operation of the present cytometer on a chip does not require fluorescent labeling of cells, stringent optical alignment, or flow through a narrow orifice. The basic principle of operation of the cytometer on a chip also reduces the complexity, mass, and power of the associated laser and detection systems, relative to those needed in conventional flow cytometry. Instead of making cells flow in single file through a narrow flow orifice for sequential interrogation as in conventional flow cytometry, a liquid containing suspended sampled cells is made to flow over the front surface of a microarray chip on which there are many capture spots. Each capture spot is coated with a thin (.50-nm) layer of gold that is, in turn, coated with antibodies that bind to cell-surface molecules characteristic of the cell species of interest. The multiplicity of capture spots makes it possible to perform rapid, massively parallel analysis of a large cell population. The binding of cells to each capture spot gives rise to a minute change in the index of refraction at the surface of the chip. This change in the index of refraction is what is sensed in GCSPRI, as described briefly below. The identities of the various species in a sample of cells is spatially encoded in the chip by the pattern of capture spots. The number of cells of a particular species is determined from the magnitude of the GCSPRI signal from that spot. GCSPRI as used here can be summarized as follows: The cytometer chip is fabricated with a diffraction grating on its front surface. The chip is illuminated with a light emitting diode (LED) from the front. By proper choice of grating parameters and of the wavelength and the angle of incidence of a laser beam, laser light can be made to be coupled into an electromagnetic mode that resonates with surface plasmons and thus couples light into surface plasmons. Coupling of light into a surface plasmon at a given location reduces the amount of incident light reflected from that location. A change in the index of refraction at the surface of a capture spot gives rise to a change in the resonance condition. Depending on the specific design, the change in the index of refraction could manifest itself as a brightening or darkening, a change in the wavelength needed to excite the plasmon at a given angle of incidence, or a change in the angle of incidence needed to excite the plasmon at a given wavelength. Whereas a multiwavelength laser system with multichannel detection would be needed to detect multiple species in conventional flow cytometry, it suffices to use an LED and a single detector channel in the GCSPRI approach: this contributes significantly to reductions in cost, complexity, size, mass, and power. GCSPRI cytometer chips could be made of plastic and could be mass-produced cheaply by use of molding and other methods adopted from the manufacture of digital video disks. These methods are amenable to a high degree of miniaturization: such additional features as fluidic channels, reaction chambers, and fluid-coupling ports could readily be incorporated into the chips, without incurring substantial additional costs.

Fernandez, Salvador M.↗

NASA NTRS2011

Cytometer on a Chip

A cytometer now under development exploits spatial sorting of sampled cells on a microarray chip followed by use of grating-coupled surface-plasmon-resonance imaging (GCSPRI) to detect the sorted cells. This cytometer on a chip is a prototype of contemplated future miniature cytometers that would be suitable for rapidly identifying pathogens and other cells of interest in both field and laboratory applications and that would be attractive as alternatives to conventional flow cytometers. The basic principle of operation of a conventional flow cytometer requires fluorescent labeling of sampled cells, stringent optical alignment of a laser beam with a narrow orifice, and flow of the cells through the orifice, which is subject to clogging. In contrast, the principle of operation of the present cytometer on a chip does not require fluorescent labeling of cells, stringent optical alignment, or flow through a narrow orifice. The basic principle of operation of the cytometer on a chip also reduces the complexity, mass, and power of the associated laser and detection systems, relative to those needed in conventional flow cytometry. Instead of making cells flow in single file through a narrow flow orifice for sequential interrogation as in conventional flow cytometry, a liquid containing suspended sampled cells is made to flow over the front surface of a microarray chip on which there are many capture spots. Each capture spot is coated with a thin (approximately 50-nm) layer of gold that is, in turn, coated with antibodies that bind to cell-surface molecules characteristic of one the cell species of interest. The multiplicity of capture spots makes it possible to perform rapid, massively parallel analysis of a large cell population. The binding of cells to each capture spot gives rise to a minute change in the index of refraction at the surface of the chip. This change in the index of refraction is what is sensed in GCSPRI, as described briefly below. The identities of the various species in a sample of cells is spatially encoded in the chip by the pattern of capture spots. The number of cells of a particular species is determined from the magnitude of the GCSPRI signal from that spot. GCSPRI as used here can be summarized as follows: The cytometer chip is fabricated with a diffraction grating on its front surface. The chip is illuminated with a light emitting diode (LED) from the front. By proper choice of grating parameters and of the wavelength and the angle of incidence of a laser beam, laser light can be made to be coupled into an electromagnetic mode that resonates with surface plasmons and thus couples light into surface plasmons. Coupling of light into a surface plasmon at a given location reduces the amount of incident light reflected from that location. A change in the index of refraction at the surface of a capture spot gives rise to a change in the resonance condition. Depending on the specific design, the change in the index of refraction could manifest itself as a brightening or darkening, a change in the wavelength needed to excite the plasmon at a given angle of incidence, or a change in the angle of incidence needed to excite the plasmon at a given wavelength. Whereas a multiwavelength laser system with multichannel detection would be needed to detect multiple species in conventional flow cytometry, it suffices to use an LED and a single detector channel in the GCSPRI approach: this contributes significantly to reductions in cost, complexity, size, mass, and power. GCSPRI cytometer chips could be made of plastic and could be mass-produced cheaply by use of molding and other methods adopted from the manufacture of digital video disks. These methods are amenable to a high degree of miniaturization: such additional features as fluidic channels, reaction chambers, and fluid-coupling ports could readily be incorporated into the chips, without incurring substantial additional costs.

Fernandez, Salvador M.↗

NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗

DOE OSTI2023

Microfluidic systems, pumps, valves, fluidic chips thereof, and applications of same

Microfluidic systems, pumps, valves and applications of the same are provided. The microfluidic system may be a pump or a valve having a fluidic chip and an actuator controlling the opening and closing of the fluidic channel in the fluidic chip. The actuator may be disposed to tilt from the fluidic chip, forming a tilted-rotor peristaltic pump. Alternatively, the actuator may be a rolling ball actuator, and different fluidic chips may be used in different applications. For example, the fluidic chip may be a spiral pump chip having spiral channels, a rotary peristaltic pump chip having multiple output channels, or a multi-port valve chip having one port interconnected with multiple different ports. An analytical valve chip may switchably interconnect bioreactor and rinse/calibration input channels to sensor and waste output channels. The actuator of a random-access valve can move from one valve position to another without opening or closing intermediate ones.

Reiserer, Ronald S.↗

DOE OSTI2023

Microfluidic systems, pumps, valves, fluidic chips thereof, and applications of same

Reiserer, Ronald S.↗

NASA NTRS1993

Ignition propagation and heat effects of propellant chips embedded in castable inhibitor using a laser flux test bomb

A castable inhibitor is applied to the aft face of the Space Shuttle Redesigned Solid Rocket Motor (RSRM) forward segment propellant grain to control propellant surface burn area. During fabrication, the propellant surface is trimmed prior to the inhibitor application. This produces a potential for small propellant chips to remain undetected on the propellant surface and contaminate the inhibitor during application. The concern was that undetected propellant chips in the inhibitor might provide a fuse path for premature propellant ignition underneath the inhibitor. To evaluate the fuse path potential, testing was performed on inhibitor samples with embedded propellant. The internal motor environment was simulated with a calibrated CO2 laser beam directed onto a sample which was placed in a 4100 kPa (600 psi) nitrogen pressurized bomb (laser bomb). The testing showed definitive results pertaining to fuse path formation. Embedded propellant chips did not autoignite until the receding heat affected inhibitor surface reached, or passed, the propellant chip. Samples with embedded propellant chips in alignment did not propagate ignition from one chip to another with separation distances as small as 0.010 cm(0.004 inc) and some as little as 0.0051 cm (0.002 in). Propellant chips with volumes approximately less than 0.025 cu cm (0.0015 cu in) (which did not propagate ignition) did not increase the inhibitor material decomposition depth more than the resulting void cavity of the burned out propellant chip. In addition, the depth of this void cavity did not increase until it was overtaken by the surrounding material decomposition depth. This was due, in part, to the retention of the protective inhibitor char layer. Samples with embedded propellant strings, whose thicknesses were below 0.023 cm (0.009 in), did not propagate ignition. Propellant string thicknesses above 0.038 cm (0.015 in) did propagate ignition. Test sample char and heat affected layer measurements and observations compared well with those from the Space Shuttle Solid Rocket Motor (SRM) Technical Evaluation Motor no. 9(TEM-9).

Bolton, Douglas E., Jr.↗

NASA NTRS2003

Experiences with Lab-on-a-chip Technology in Support of NASA Supported Research

Under the auspices of the Microgravity Sciences and Application Department at Marshall Space Flight Center, we have custom designed and fabricated a lab-on-a-chip (LOC) device, along with Caliper Technologies, for macromolecular crystal growth. The chip has been designed to deliver specified proportions of up-to five various constituents to one of two growth wells (on-chip) for crystal growth. To date, we have grown crystals of thaumatin, glucose isomerase and appoferitin on the chip. The LOC approach offered many advantages that rendered it highly suitable for space based hardware to perform crystal growth on the International Space Station. The same hardware that was utilized for the crystal growth investigations, has also been used by researchers at Glenn Research Center to investigate aspects of microfluidic phenomenon associated with two-phase flow. Additionally, our LOCAD (Lab-on-a-chip Application Development) team has lent its support to Johnson Space Center s Modular Assay for Solar System Exploration project. At present, the LOCAD team is working on the design and build of a unique lab-on-a-chip breadboard control unit whose function is not commercially available. The breadboard can be used as a test bed for the development of chip size labs for environmental monitoring, crew health monitoring assays, extended flight pharmacological preparations, and many more areas. This unique control unit will be configured for local use and/or remote operation, via the Internet, by other NASA centers. The lab-on-a-chip control unit is being developed with the primary goal of meeting Agency level strategic goals.

Monaco, Lisa↗

NASA NTRS1988

Programmable synaptic chip for electronic neural networks

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Moopenn, A.↗

NASA NTRS1992

Design and qualification of the SEU/TD Radiation Monitor chip

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Buehler, Martin G.↗

NASA NTRS2001

Chip packaging technique

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Jayaraj, Kumaraswamy↗

NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗

DOE OSTI2026

Directional dependence of equilibrated TLD-400 chips in multiple radiation fields

Fielding of thermoluminescent dosimeters (TLDs) for measurement of photon radiation dose in experiments is the standard practice for γ-irradiation facilities, pulsed power x-ray facilities, and reactor facilities at Sandia National Laboratories (SNL). Due to the high-dose experimental conditions and the mixed ( 1 n, γ) fields in these facilities, SNL radiation metrologists have historically used CaF 2 :Mn TLDs (also known as TLD-400). Recent inquiries to the radiation metrology staff have raised concerns that the aluminum-equilibrated TLD-400 chips may exhibit a directionally dependent response. The metrologists were asked whether the dose measured by the chip may be impacted by the angle of incidence on the equilibrated TLD. To provide a thorough answer to this query, a set of adjoint Monte Carlo radiation transport calculations was performed for three different equilibrated TLDs as well as bare TLD chips using the Integrated Tiger Series (ITS) code. The key feature of the adjoint calculations performed in this study is that each photon escaping the modeled geometry was tallied into angular bins to provide information on both the energy and angular dependence of the equilibrated chip. After the adjoint Monte Carlo calculations were completed, the resulting energy-dependent response function for each angular bin was convolved with multiple photon energy spectra representing various radiation facilities at SNL. The radiation facilities selected for analysis span a range of photon energies from approximately 1 keV up to approximately 20 MeV. Thus, the presented results are applicable to a wide variety of radiation facilities around the world. Although the bare TLD-400 chip was expected to display the largest variation due to the photon angle of impact on the dosimeter, the dosimeter with the thinnest aluminum equilibrator (SNL thin equilibrated TLD-400) was determined to have the biggest differential between the impact angle with the maximum dose ( D max ) and the impact angle with the minimum dose ( D min ). However, the SNL normal equilibrated TLD-400 chip demonstrated a dramatic reduction in that differential between maximum and minimum dose angles. The reduction in this differential is one of the dominant factors in experimenters’ choice to field these dosimeters at SNL radiation facilities. The results from the PNNL (Hanford) energy-flattening field capsule are consistent with the previous publications. The differential dose responses due to the photon impact angle indicate that experimenters should strive to field their TLD-400 dosimeters in a consistent manner to avoid additional uncertainty in the measurements based on dosimeter orientation.

Adjoint radiation transport↗

DOE OSTI2024

Atom-resolved imaging with a silicon tip integrated into an on-chip scanning tunneling microscope

Limited throughput is a shortcoming of the Scanning Tunneling Microscope (STM), particularly when used for atomically precise lithography. To address this issue, we have developed an on-chip STM based on Microelectromechanical-Systems (MEMS) technology. The device reported here has one degree of freedom, replacing the Z axis in a conventional STM. The small footprint of the on-chip STM provides a great opportunity to increase STM throughput by incorporating a number of on-chip STMs in an array to realize parallel STM. The tip methodology adopted for the on-chip STM presented here, which is a batch-fabricated Si tip, makes our design conducive to this goal. In this work, we investigate the capability of this on-chip STM with an integrated Si tip for STM imaging. We integrate the on-chip STM into a commercial ultrahigh-vacuum STM system and perform imaging with atomic resolution on par with conventional STMs but at higher scan speeds due to the higher sensitivity of the MEMS actuator relative to a piezotube. The results attest that it is possible to achieve a parallel and high-throughput STM platform, which is a fully batch-fabricated MEMS STM nanopositioner capable of performing atomic-resolution STM imaging.

Instruments & Instrumentation↗