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Results for “Chip-Scale Capacitors”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2013

Integrated Power Chip Converter for Solid State Lighting (Final Report)

The overall goal of the project was to develop an integrated power converter chip for solid-state lighting. We developed a low component count circuit topology, fast and low loss switching devices, compact and low loss passive components, and integration methodology to enable an integrated LED driver, where cost, size and efficiency are paramount. The converter was designed to operate directly from ac line voltage, nominally providing 24 V output at 25 W with features of dimming and control for light uniformity. We developed a power circuit and control suitable for chip-scale integration, low loss and high frequency GaN power devices with a new vertical architecture that reduces parasitics and lowers cost by decreasing the chip real estate, and high-density passives, including a chip-scale flyback transformer that integrates inductor and transformer action into a single component.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

Optics-Free Chip-Scale Intraoperative Imaging Using NIR-Excited Upconverting Nanoparticles

Here we present an optics-free CMOS image sensor that incorporates a novel time-gated dual-photodiode pixel design to allow filter- and lens-less image acquisition of near-infrared-excited (NIR-excited) upconverting nanoparticles. Recent biomedical advances have highlighted the benefits of NIR excitation, but NIR interaction with silicon has remained a challenge, even with high-performance optical blocking filters. Using a secondary diode and a dual-photodiode design, this sensor is able to remove the 100s of mV of NIR background on pixels and bring it down to single-digit mV level, nearing its noise floor of 2.2 mV rms, not achievable with any optical filter. Non-linear effects of background cancellation using the diode pair has been mitigated using an initial one-time pixel-level curve fitting and calibration in a post-processing setting. This imager comprises a highly linear 11 fF metal-oxide-metal (MOM) capacitor and includes integrated angle-selective gratings to reject oblique light and enhance sharpness. Each pixel also includes two distinct correlated double sampling schemes, to remove low frequency flicker noise and systematic offset in the datapath. We demonstrate the performance of this imager using pulsed NIR-excited upconverting nanoparticles on standard United-States-Air-Force (USAF) resolution targets and achieve an SNR of 15 dB, while keeping NIR background below 6 mV. This 36-by-80-pixel array measures only 2.3 mm by 4.8 mm and can be thinned down to 25 µm, allowing it to become surgically compatible with intraoperative instruments and equipment, while remaining optics-free.

42 ENGINEERING↗