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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

A Novel Spatial-Temporal Variational Quantum Circuit to Enable Deep Learning on NISQ Devices

Quantum computing presents a promising approach for machine learning with its capability for extremely parallel computation in high-dimension through superposition and entanglement. Despite its potential, existing quantum learning algorithms, such as Variational Quantum Circuits (VQCs), face challenges in handling more complex datasets, particularly those that are not linearly separable. What’s more, it encounters the deployability issue, making the learning models suffer a drastic accuracy drop after deploying them to the actual quantum devices. To overcome these limitations, this paper proposes a novel spatial-temporal design, namely “ST-VQC”, to integrate nonlinearity in quantum learning and improve the robustness of the learning model to noise. Specifically, ST-VQC can extract spatial features via a novel block-based encoding quantum sub-circuit coupled with a layer-wise computation quantum sub-circuit to enable temporal-wise deep learning. Additionally, a SWAP-Free physical circuit design is devised to improve robustness. These designs bring a number of hyperparameters. After a systematic analysis of the design space for each design component, an automated optimization framework is proposed to generate the ST-VQC quantum circuit. The proposed ST-VQC has been evaluated on two IBM quantum processors, ibm-cairo with 27 qubits and ibmq-lima with 7 qubits to assess its effectiveness. The results of the evaluation on the standard dataset for binary classification show that ST-VQC can achieve over 30% accuracy improvement compared with existing VQCs on actual quantum computers. Moreover, on a non-linear synthetic dataset, the STVQC outperforms a linear classifier by 27.9%, while the linear classifier using classical computing outperforms the existing VQC by 15.58%.

Li, Jinyang↗
DOE OSTI2020

Setting operating points for circuits in an integrated circuit chip using an integrated voltage regulator power loss model

An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

42 ENGINEERING↗
NASA NTRS1983

Design of low loss helix circuits for interference fitted and brazed circuits

The RF loss properties and thermal capability of brazed helix circuits and interference fitted circuits were evaluated. The objective was to produce design circuits with minimum RF loss and maximum heat transfer. These circuits were to be designed to operate at 10 kV and at 20 GHz using a gamma a approximately equal to 1.0. This represents a circuit diameter of only 0.75 millimeters. The fabrication of this size circuit and the 0.48 millimeter high support rods required considerable refinements in the assembly techniques and fixtures used on lower frequency circuits. The transition from the helices to the waveguide was designed and the circuits were matched from 20 to 40 GHz since the helix design is a broad band circuit and at a gamma a of 1.0 will operate over this band. The loss measurement was a transmission measurement and therefore had two such transitions. This resulting double-ended match required tuning elements to achieve the broad band match and external E-H tuners at each end to optimize the match for each frequency where the loss measurement was made. The test method used was a substitution method where the test fixture was replaced by a calibrated attenuator.

Jacquez, A.↗
NASA NTRS1999

Gate drive latching circuit for an auxiliary resonant commutation circuit

A gate drive latching circuit for an auxiliary resonant commutation circuit for a power switching inverter includes a current monitor circuit providing a current signal to a pair of analog comparators to implement latching of one of a pair of auxiliary switching devices which are used to provide commutation current for commutating switching inverters in the circuit. Each of the pair of comparators feeds a latching circuit which responds to an active one of the comparators for latching the associated gate drive circuit for one of the pair of auxiliary commutating switches. An initial firing signal is applied to each of the commutating switches to gate each into conduction and the resulting current is monitored to determine current direction and therefore the one of the switches which is carrying current. The comparator provides a latching signal to the one of the auxiliary power switches which is actually conducting current and latches that particular power switch into an on state for the duration of current through the device. The latching circuit is so designed that the only time one of the auxiliary switching devices can be latched on is during the duration of an initial firing command signal.

Delgado, Eladio Clemente↗
DOE OSTI2022

An Innovative Circuit Breaker for Renewable Power Grids

A key step towards a carbon-neutral future could be reached through dispersed power grids, featuring networks of local-scale renewable energy and battery storage plants. To prevent these power grids from damaging themselves and their surroundings when electrical faults arise, they must be integrated with ‘circuit breakers’, which temporarily interrupt the current flowing through them. However, currently available circuit breakers cannot handle the medium-voltage direct currents best suited for these grids. Through an innovative new circuit breaker design, Steve Schmalz and his colleagues at Eaton Corporation, the Illinois Institute of Technology (IIT), Virginia Tech and the National Energy Technology Laboratory (NETL), hope that this challenge will soon be overcome.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

Possibilistic simulation of quantum circuits by classical circuits

In a breakthrough work, Bravyi, Gosset, and König (BGK) [Science 362, 308 (2018)] unconditionally proved that constant-depth quantum circuits are more powerful than their classical counterparts. Here, their result is equivalent to saying that a particular family of constant-depth quantum circuits takes classical circuits at least Ω⁡(log⁡n) depth to “simulate,” in a certain sense. In our paper, we formalize their sense of simulation, which we call “possibilistic simulation” or “p-simulation,” and construct explicit classical circuits that can p-simulate any depth-d quantum circuit with Clifford and t T-gates in depth O(d+t). Our classical circuits use {NOT,AND,OR} gates of fan-in ≤ 2.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2020

HEMP Testing of Substation Yard Circuit Breaker Control and Protective Relay Circuits

There are concerns about the effects of High-Altitude Electromagnetic Pulses (HEMP) on the electric power grid. Activities to date tested and analyzed vulnerability of digital protective relays (DPRs) used in power substations, but the effect of HEMP on the greater substation environment is not well known. This work establishes a method of testing the vulnerability of circuit breaker control and protective relay circuits to the radiated E1 pulse associated with HEMP based on coupling to the cables in a substation yard. Two DPRs from Schweitzer Engineering Laboratories, Inc. were independently tested. The test setup also included a typical cable in a substation yard with return plane to emulate the ground grid and other ground conductors near the yard cable, cabinetry housing the installed DPRs, station battery and battery charger, terminal block elements, and a breaker simulator to emulate a substation yard configuration. The DPRs were powered from the station battery and the transformer inputs energized with a three-phase source to maintain typical operating conditions during the tests. Vulnerability testing consisted of a conducted E1 pulse injected into the center of the yard cable of the DPR circuits. Current measurements on the yard cable and DPR inputs indicated significant attenuation of the conducted pulse arriving at the control house equipment from the emulated substation yard. This reduction was quantified with respect to the equivalent open-circuit voltage on the yard cable. No equipment damage or undesired operation occurred on the tested circuits for values below 180 kV, which is significantly higher than the anticipated coupling to a substation yard cable.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1990

Statistical circuit design for yield improvement in CMOS circuits

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.↗
NASA NTRS2016

Method and Circuit for Injecting a Precise Amount of Charge onto a Circuit Node

A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.

Hancock, Bruce R.↗
DOE OSTI2024

Quantum Circuit Partitioning for Scalable Noise-Aware Quantum Circuit Re-Synthesis

Re-synthesis techniques are utilized to optimize the quantum circuit. To enable scalable re-synthesis a divide-and-conquer approach is adopted that partitions the circuit into smaller blocks, which are optimized independently. Several algorithms have been proposed to minimize the block number while maximizing the gate count of each block. However, they vary in their performance and may not yield the highest output fidelity. We propose a reinforcement learning-based quantum circuit partitioning framework that incorporates the physical properties of the quantum hardware to maximize the output fidelity post-quantum circuit optimization. To accelerate the training, we also propose a noise injection method that enables on-the-fly optimization in the reinforcement learning environment, independent of the adopted optimization/re-synthesis method at the block level. We evaluate our approach compared to different partitioning techniques using various quantum benchmarks executed on IBM Q Hanoi quantum computer.

Charrwi, Mohammad Walid↗
NASA NTRS1991

An Investigative Redesign of the ECG and EMG Signal Conditioning Circuits for Two-fault Tolerance and Circuit Improvement

An investigation was undertaken to make the elctrocardiography (ECG) and the electromyography (EMG) signal conditioning circuits two-fault tolerant and to update the circuitry. The present signal conditioning circuits provide at least one level of subject protection against electrical shock hazard but at a level of 100 micro-A (for voltages of up to 200 V). However, it is necessary to provide catastrophic fault tolerance protection for the astronauts and to provide protection at a current level of less that 100 micro-A. For this study, protection at the 10 micro-A level was sought. This is the generally accepted value below which no possibility of microshock exists. Only the possibility of macroshock exists in the case of the signal conditioners. However, this extra amount of protection is desirable. The initial part deals with current limiter circuits followed by an investigation into the signal conditioner specifications and circuit design.

Obrien, Edward M.↗
NASA NTRS2011

Fast-responding short circuit protection system with self-reset for use in circuit supplied by DC power

A short circuit protection system includes an inductor, a switch, a voltage sensing circuit, and a controller. The switch and inductor are electrically coupled to be in series with one another. A voltage sensing circuit is coupled across the switch and the inductor. A controller, coupled to the voltage sensing circuit and the switch, opens the switch when a voltage at the output terminal of the inductor transitions from above a threshold voltage to below the threshold voltage. The controller closes the switch when the voltage at the output terminal of the inductor transitions from below the threshold voltage to above the threshold voltage.

Burns, Bradley M.↗
NASA NTRS1972

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Source record↗
NASA NTRS2008

Circuit with a Switch for Charging a Battery in a Battery Capacitor Circuit

A circuit for charging a battery combined with a capacitor includes a power supply adapted to be connected to the capacitor, and the battery. The circuit includes an electronic switch connected to the power supply. The electronic switch is responsive to switch between a conducting state to allow current and a non-conducting state to prevent current flow. The circuit includes a control device connected to the switch and is operable to generate a control signal to continuously switch the electronic switch between the conducting and non-conducting states to charge the battery.

Stuart, Thomas A.↗
DOE OSTI2022

Autonomous Microgrid Restoration Using Grid-Forming Inverters and Smart Circuit Breakers

The proliferation of distributed inverter-based resources (IBRs) raises the questions if these IBRs can be used to blackstart microgrids and distribution feeders after major outages. In this paper, we propose and evaluate an autonomous microgrid restoration concept using grid-forming (GFM) IBRs and smart circuit creakers (SCBs). The concept is first explored in simulation platform and then a hardware testbed containing actual GFM inverters is developed to demonstrate these functionalities. A combination of dispatchable virtual oscillator control (dVOC) and droop-based control schemes have been designed for GFM inverter controls in the software simulations and hardware testbed. Subsequently, operation of SCBs using two distinct principles have been demonstrated that can restore or connect portions of the network.

black start↗
DOE OSTI2024

Open Circuit Potential Method for Thermodynamic Hydricity Measurements of Metal Hydrides

Metal hydrides are prevalent in many catalytic reactions, and thermodynamic hydricity has emerged as a useful parameter for understanding and predicting key hydride transfer steps with these intermediates. An open circuit potentiometry method for determining the hydricity of metal hydrides with a single thermodynamic parameter is reported. The open circuit potential (OCP) of a solution containing a metal hydride and its conjugate hydride acceptor, along with a conjugate acid/base pair, is coupled with known values for the acid pK a and H + /H – reduction potential to determine the hydricity. Here, the reliability of the method was established by using potentiometry to obtain the hydricity of three hydride complexes with varying supporting ligands and transition metal elements in acetonitrile solvent, all within error of previously reported values. Advantages and drawbacks of this method are discussed, and a recommended workflow for practitioners is introduced.

Anions↗
DOE OSTI2022

System-on-chip integrated circuit technology applications on the DIII-D tokamak for multi-field measurements

Several mm-wave diagnostics on the DIII-D tokamak provide multi-scale and multi-dimensional measurements of plasma profile evolution and turbulence fluctuations. Mm-wave fusion plasma diagnostics that adopt system-on-chip integrated circuit technology can provide better space utilization, flexible installation, and improved sensitivity. In order to further extend this technology for additional fusion facilities with a higher toroidal magnetic field, V-band (55–75 GHz) and F-band (90–140 GHz) chips for Microwave Imaging Reflectometer (MIR) and Electron Cyclotron Emission Imaging (ECEI) instruments are developed and tested in the Davis Millimeter Wave Research Center (DMRC). Current measurement data show that correlation between these SoC-based diagnostic instruments with other state-of-the-art diagnostics enables co-located multi-field turbulence fluctuation measurement.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗