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Results for “Complementary Metal Oxide Semiconductor (CMOS)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Phase Synergy Enables Low‐Power Ferroelectric Switching in HfO 2 Epitaxial Films

HfO 2 -based ferroelectric materials have emerged as leading candidates for next-generation non-volatile memory technologies, owing to their nanoscale robust ferroelectricity and complementary metal–oxide–semiconductor (CMOS) compatibility. However, challenges and debates persist in advancing and comprehensively understanding their ferroelectric behavior. In particular, conventional approaches typically regard non-ferroelectric phases as detrimental and primarily focus on suppressing their formation, yet overlooking their potentially synergistic contributions—particularly those of the tetragonal (T) phase. Here, we unambiguously clarify the beneficial role of the T-phase and introduce a phase-boundary engineering strategy that deliberately harnesses it to enhance ferroelectricity in HfO 2 films. By stabilizing optimal coherent boundaries between ferroelectric orthorhombic (O) and T phases in epitaxial La-doped HfO 2 films, we achieve significant improvements in ferroelectric properties—doubling the remanent polarization (P r ∼ 30 µC/cm 2 ) and substantially reducing the coercive field (E c ∼ 3 MV/cm) by 30% compared to low-La doped samples without such boundaries. Atomic-scale electron microscopy reveals the structural nature of the atomically sharp, coherent O–T boundaries. Combined with deep-learning enhanced molecular dynamics simulations, our results unravel that these boundaries facilitate intermediate polarization states that lower the switching energy barrier. Consequently, phase coexistence shifts from an inherent drawback to a tunable design element, offering a broadly applicable route to ultra-low-power HfO 2 -based nanoelectronics.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

Nanophotonic waveguide chip-to-world beam scanning

A seamless chip-to-world photonic interface enables broad advancements in optical ranging, display, communication, computation and quantum information science. The ideal solution enables two-dimensional scanning of a diffraction-limited beam from anywhere on a photonic integrated circuit to a large number of resolvable spots. Current beam-scanning technologies are limited by a fundamental trade-off: photonic-integrated-circuits with diffractive optics offer scalability but have poor mode quality, whereas inertially limited micromechanical scanners provide high-quality beams but lack scalable integration. Here we report a photonic ski-jump—a nanoscale waveguide monolithically integrated on a piezoelectric cantilever—to overcome these limitations. It passively curls ~90° out-of-plane within a less-than-0.1 mm 2 footprint, emits a submicrometre, broadband diffraction-limited beam, and exhibits kilohertz-rate mechanical resonances with quality factors of over 10,000. Fabricated in a volume complementary metal–oxide–semiconductor (CMOS) foundry, our device enables scalable two-dimensional beam scanning. Driven on-resonance at CMOS-level voltages, it achieves a footprint-adjusted spot rate of 68.6 mega spots s –1 mm–², exceeding state-of-the-art micro-electro-mechanical systems mirrors by more than 50-fold, which is sufficient for one million pixels at 100 Hz from an approximately 1.5 mm diameter footprint. We demonstrate full-colour image and video projection, and single-photon initialization and readout from silicon vacancy centres in diamond. Finally, by demonstrating uniformity across a 64 ski-jump array, we establish a pathway to achieving greater than one gigaspot resolution at kilohertz rates within a sub-5-cm-diameter footprint, creating a seamless optical pipeline between integrated photonic processors and the free-space world.

Displays↗
DOE OSTI2025

Perspectives of active Si photonics devices for data communication and optical sensing

Si photonics has made rapid progress in research and commercialization in the past two decades. While it started with electronic–photonic integration on Si to overcome the interconnect bottleneck in data communications, Si photonics has now greatly expanded into optical sensing, light detection and ranging (LiDAR), optical computing, and microwave/RF photonics applications. From an applied physics point of view, this perspective discusses novel materials and integration schemes of active Si photonics devices for a broad range of applications in data communications, spectrally extended complementary metal–oxide–semiconductor (CMOS) image sensing, as well as 3D imaging for LiDAR systems. We also present a brief outlook of future synergy between Si photonic integrated circuits and Si CMOS image sensors toward ultrahigh capacity optical I/O, ultrafast imaging systems, and ultrahigh sensitivity lab-on-chip molecular biosensing.

electronic band structure↗
DOE OSTI2024

Soft X-ray quantum efficiency of a commercial CMOS imaging sensor

The demonstrated performance and cost-effectiveness of complementary metal-oxide-semiconductor (CMOS) sensors make them a potentially attractive option for low-cost space-based X-ray observatories. We have previously reported on the performance of a commercially available backside-illuminated Sony IMX290LLR-C CMOS sensor and found it to offer X-ray spectral resolutions comparable to the charged coupled devices (CCDs) aboard Suzaku and Chandra and to have a sufficient radiation hardness for use in low Earth orbit. Here, in this work, we report on the quantum efficiency (QE) of this sensor, an essential metric for modeling the sensitivity of an instrument as an X-ray detector. Using the Advanced Photon Source at Argonne National Laboratory, we measure the soft X-ray QE of this CMOS sensor to be 0.28 ± 0.02 at a photon energy of 490.5 eV. This energy was chosen for its proximity to the astrophysically important O VII triplet emission lines (~574 eV) studied by the HaloSat mission. Although not surpassing that of the back-illuminated CCDs aboard Suzaku and Chandra, this QE compares favorably to that of the front-illuminated CCDs aboard the same observatories and is competitive with that of the silicon drift detectors used aboard HaloSat, making it a strong candidate for use on future X-ray small satellite (SmallSat) missions.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Reconfigurable Cascaded Thermal Neuristors for Neuromorphic Computing

While the complementary metal-oxide semiconductor (CMOS) technology is the mainstream for the hardware implementation of neural networks, an alternative route is explored based on a new class of spiking oscillators called “thermal neuristors”, which operate and interact solely via thermal processes. Utilizing the insulator-to-metal transition (IMT) in vanadium dioxide, a wide variety of reconfigurable electrical dynamics mirroring biological neurons is demonstrated. Notably, inhibitory functionality is achieved just in a single oxide device, and cascaded information flow is realized exclusively through thermal interactions. To elucidate the underlying mechanisms of the neuristors, a detailed theoretical model is developed, which accurately reflects the experimental results. In conclusion, this study establishes the foundation for scalable and energy-efficient thermal neural networks, fostering progress in brain-inspired computing.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Rapid spatial analysis of surrogate TRISO fuel particles using laser-induced breakdown spectroscopy image analysis

Laser-induced breakdown spectroscopy (LIBS) mapping enables rapid elemental and spatial analysis of solid samples. In this work, surrogate TRi-structural ISOtropic (TRISO) particles with various layers consisting of Zr, W, C, and Si were used to demonstrate the use of a new thickness measurement tool developed to analyze elemental images generated from LIBS maps. Zr particles with varying outer-layer thicknesses ranging from 16 to 32 μm were measured with scanning electron microscopy with energy dispersive spectroscopy (SEM-EDS) and LIBS with both a complementary metal-oxide-semiconductor (CMOS) detector and an intensified charged coupled device (ICCD) detector. LIBS maps of particles were completed using CMOS and ICCD spectrometers with effective spatial resolutions of 4 and 2 μm, respectively. The novel thickness measurement tool identified layer regions within a LIBS map and then identified the locations of the boundaries between these layers. The tool then generated up to 1000 random profiles stemming radially from the center region, which were used to measure the layer thickness/radius. This image analysis tool demonstrated LIBS's ability to provide values comparable with SEM-EDS (3.7% relative difference) along with a 95% reduction in measurement time. Furthermore, the precision of these measurements was on par with the SEM-EDS measurements at <15% relative standard deviation. Following the analysis of the Zr particles, W particles with increased complexity (e.g., five versus three layers) were analyzed using both the CMOS and ICCD spectrometers simultaneously. The spatial dimensions were extracted with an average relative difference of 2.7% and an average relative standard deviation of 9%.

Andrews, Hunter B. [Oak Ridge National Laboratory ↗
DOE OSTI2026

Knowledge gaps for neuromorphic ionic computing

BACKGROUND Neuromorphic computing, inspired by the human brain’s ability to process information efficiently, represents a transformative approach to computation. In this Review, we explore the emerging field of neuromorphic ionic computing, which leverages ionic conduction and coupling to mimic neural processes, and identify critical knowledge gaps that must be addressed to realize its full potential. A central theme of the discussion is energy efficiency, a challenge that is both a limitation and an opportunity for this technology. Although complementary metal-oxide semiconductor (CMOS)–based neuromorphic technologies have made strides in scaling to billions of neurons and are increasingly applied in artificial intelligence and numerical computing, they remain orders of magnitude behind the human brain in terms of connectivity and energy efficiency. Neuromorphic ionic computing promises to overcome these limitations by leveraging the distinct architectural and operational principles of the brain. Our brains achieve this energy efficiency by combining several key features: using the same network elements to store and process information; using an incredibly complex and massively interconnected three-dimensional (3D) network of locally active elements that enables sparsity, robustness in the presence of noise, adaptation, and life-long learning; computing at comparatively low voltage and frequency; and last, taking advantage of a plethora of ions and small molecules as information carriers. Here, we propose that ionic computing systems can take advantage of similar features to achieve substantial gains in energy efficiency. ADVANCES Since the first reports of neuromorphic ionic behavior in nanofluidic channels, we have witnessed an explosion of reports that used ionic devices to produce synaptomimetic behaviors. However, achieving the goals of ionic computing requires not only implementation of much more sophisticated device functionality but also overcoming fundamental barriers in materials science, device architecture, and system integration. Current ionic devices, even those incorporating state-of-the-art materials, still suffer from limited functionality and stability, which restrict their performance and increase energy demands. Developing new materials with enhanced ionic properties is essential to overcome these limitations. Similarly, the design of neuromorphic devices must evolve to leverage the particular advantages of ionic processes. Existing architectures often follow a single-information-carrier logic of conventional electronics or are constructed of mesoscale fluidics, failing to capitalize on the energy-efficient mechanisms inherent to ionic systems or implement the multiple-information-carrier paradigm. Current neuromorphic chips focus on large-scale networks of analog memory elements based on mechanisms such as charge trap (flash), filamentary, phase change, or spin, which are built on top of a network of artificial CMOS neurons. Although such prototype networks have achieved impressive performance, it is difficult to envision how they can implement the key features such as massive connectivity, sophisticated plasticity, adaptability, sparsity, and “multichromatic” computing. Although small-scale devices have demonstrated promising results, integrating them, maintaining energy efficiency, and implementing temperature control as systems grow in complexity and size to computationally relevant scale remain major hurdles. Furthermore, interfacing neuromorphic ionic devices with existing computing technologies presents technical and conceptual challenges that will require innovative approaches that combine insights from neuroscience, materials science, and engineering. OUTLOOK Despite these challenges, the potential impact of neuromorphic ionic computing is profound with potential applications ranging from artificial intelligence to robotics and beyond. We also argue that neuromorphic ionic computing systems should not, at least in the beginning, compete with CMOS technologies but rather should focus on applications that require extreme energy efficiency with chemical and/or biological compatibility, such as biomedical applications (for example, brain-computer interfaces), environmental monitoring, and agricultural and food applications. Ultimately, this Review highlights the crucial role of interdisciplinary collaboration in advancing the field. Neuromorphic ionic computing is not merely a technological innovation; it represents a substantial step toward sustainable computation, aligning with the growing demand for energy-conscious solutions in a world that is increasingly reliant on data and computation.

Neuromorphic↗
DOE OSTI2025

Telecom-to-visible quantum frequency converter on a silicon nitride chip

Quantum frequency conversion serves a key role in the realization of hybrid quantum networks by interfacing between wavelength-incompatible platforms. Here we present what is believed to be the first quantum frequency converter connecting visible and telecom domains on a silicon nitride (SiN) chip, using Bragg-scattering four-wave mixing to upconvert heralded single photons from 1260 to 698 nm, which covers a 192 THz span. We examine the noise sources in SiN and devise approaches to suppress noise photons at the source and target frequencies to enable measurements at the single-photon level. We demonstrate an on-chip conversion efficiency of 5% in photon flux and describe design modifications that can be implemented to significantly improve it. Our results pave the way for the implementation of complementary metal-oxide-semiconductor (CMOS)-compatible devices in quantum networks.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2025

Multistate resistance in TaN/(Hf,Zr)O 2 /Ta ferroelectric tunnel junctions

Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have emerged as promising non-volatile memory elements for microelectronics, compatible with back end of line (BEOL) complementary–metal–oxide semiconductor fabrication. This study investigates asymmetric electrode TaN/HZO/Ta devices with a 6 nm thick HZO layer as FTJs for multistate resistive memory applications. The individual FTJs exhibit a resistance ratio exceeding 10× when utilized as a binary state device, with pulsing between −1.7 and +1.4 V to set the high resistance state (HRS) and low resistance state (LRS), respectively. Following with reduced write voltage pulses allows the ferroelectric device to operate with a selection of over 32 distinct resistance states (2 5 bits) between the LRS and HRS. This work then explores the stability of the resistance states during write/read pulse cycling, along with the stability of the state after multiple read pulses. Accessing the multibit state shows stability within 50 reads with the binary state remaining stable for more than 4000 reads pulses. With their multistate tunability and versatility, FTJs hold promise as BEOL memory elements for compute-in-memory (CiM) arrays, binary digital memory, or weighted vector matrix multiplication applications with low power consumption during computations.

CMOS↗