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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

SPP: A data base processor data communications protocol

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

Fishwick, P. A.↗
NASA NTRS1986

The SIR-C ground data system: Digital processor, data products, information flow

The SIR-C (Shuttle Imaging Radar) instrument will collect both C-Band and L-Band data with each frequency band consisting of direct (HH or VV) and cross-polarized (HV or VH) data. Considering all possible combinations as many as eight different data channels will be available for any given target area. This data will be digitized and formatted on-board for direct downlink via the Tracking and Data Relay Satellite System (TDRSS), or it will be buffered through on-board high density digital recorders for storage or transmission when TDRSS is available. The data is received by the TDRSS ground station at White Sands and is nominally relayed via DOMSAT to the high data rate recording facility at GSFC. The tapes are then shipped to JPL for processing into imagery and eventual distribution to the SIR-C investigators.

Curlander, John C.↗
NASA NTRS1987

Optical Interferometric Parallel Data Processor

Image data processed faster than in present electronic systems. Optical parallel-processing system effectively calculates two-dimensional Fourier transforms in time required by light to travel from plane 1 to plane 8. Coherence interferometer at plane 4 splits light into parts that form double image at plane 6 if projection screen placed there.

Breckinridge, J. B.↗
NASA NTRS1994

Fast, Massively Parallel Data Processors

Proposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.

Heaton, Robert A.↗
NASA NTRS1993

Embedded Data Processor and Portable Computer Technology testbeds

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

Alena, Richard↗
NASA NTRS1968

Fully automatic telemetry data processor

Satellite Telemetry Automatic Reduction System /STARS 2/, a fully automatic computer-controlled telemetry data processor, maximizes data recovery, reduces turnaround time, increases flexibility, and improves operational efficiency. The system incorporates a CDC 3200 computer as its central element.

Cox, F. B.↗
NASA NTRS1982

A microprocessor application in the MTV telemetry data processor

An engineering model of the Telemetry Data Processor monitoring and display system used by the Maneuverable Television (MTV) employed in remote inspections of the Space Shuttle has been developed, incorporating the MC 6809 microprocessor. The system acquires analog and digital signals from the MTV flyer and converts them into engineering units, formatting them in several pages according to their function. Upon request, a data page can be superimposed on the video signal from the MTV camera. In addition, the system monitors key parameters for out-of-limit conditions and flashes caution and warning messages on the selected page.

Spahn, C. J.↗
NASA NTRS1974

Data processor with conditionally supplied clock signals

Parallel data processor clock pulses are conditionally supplied to processing unit in response to relative values of binary bit of control source and binary bit derived on single lead. Use of single lead simplifies fabrication of large-scale integrated networks.

Lesniewski, R. J.↗
NASA NTRS1989

Optical backplane interconnect switch for data processors and computers

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Hendricks, Herbert D.↗
NASA NTRS1990

Balancing Loads Among Parallel Data Processors

Heuristic algorithm minimizes amount of memory used by multiprocessor system. Distributes load of many identical, short computations among multiple parallel digital data processors, each of which has its own (local) memory. Each processor operates on distinct and independent set of data in larger shared memory. As integral part of load-balancing scheme, total amount of space used in shared memory minimized. Possible applications include artificial neural networks or image processors for which "pipeline" and vector methods of load balancing inappropriate.

Baffes, Paul Thomas↗