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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Third order digital-to-analog converter

System, consisting of sample and hold digital-to-analog converter, clock circuit, sample delay circuit, initial condition circuit and interpolator circuit, improves accuracy of reconstructed analog signal without increasing sample rates.

Dotson, W. P.↗
NASA NTRS1976

First-Order-hold interpolation digital-to-analog converter with application to aircraft simulation

Those who design piloted aircraft simulations must contend with the finite size and speed of the available digital computer and the requirement for simulation reality. With a fixed computational plant, the more complex the model, the more computing cycle time is required. While increasing the cycle time may not degrade the fidelity of the simulated aircraft dynamics, the larger steps in the pilot cue feedback variables (such as the visual scene cues), may be disconcerting to the pilot. The first-order-hold interpolation (FOHI) digital-to-analog converter (DAC) is presented as a device which offers smooth output, regardless of cycle time. The Laplace transforms of these three conversion types are developed and their frequency response characteristics and output smoothness are compared. The FOHI DAC exhibits a pure one-cycle delay. Whenever the FOHI DAC input comes from a second-order (or higher) system, a simple computer software technique can be used to compensate for the DAC phase lag. When so compensated, the FOHI DAC has (1) an output signal that is very smooth, (2) a flat frequency response in frequency ranges of interest, and (3) no phase error. When the input comes from a first-order system, software compensation may cause the FOHI DAC to perform as an FOHE DAC, which, although its output is not as smooth as that of the FOHI DAC, has a smoother output than that of the ZOH DAC.

Cleveland, W. B.↗
NASA NTRS1967

Digital-to-analog converter operates from low level inputs

Circuit controls a voltage controlled oscillator from computer output binary data representing a rate at which the oscillator is to change. It operates with low level output devices such as integrated circuit registers and devices with somewhat variable output levels.

Winkelstein, R. A.↗
NASA NTRS1972

Quantization noise in digital speech

The amount of quantization noise generated in a digital-to-analog converter is dependent on the number of bits or quantization levels used to digitize the analog signal in the analog-to-digital converter. The minimum number of quantization levels and the minimum sample rate were derived for a digital voice channel. A sample rate of 6000 samples per second and lowpass filters with a 3 db cutoff of 2400 Hz are required for 100 percent sentence intelligibility. Consonant sounds are the first speech components to be degraded by quantization noise. A compression amplifier can be used to increase the weighting of the consonant sound amplitudes in the analog-to-digital converter. An expansion network must be installed at the output of the digital-to-analog converter to restore the original weighting of the consonant sounds. This technique results in 100 percent sentence intelligibility for a sample rate of 5000 samples per second, eight quantization levels, and lowpass filters with a 3 db cutoff of 2000 Hz.

Schmidt, O. L.↗
DOE OSTI2026

Captan+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗
DOE OSTI2026

CAPTAN+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗
NASA NTRS1972

A digital-to-analog conversion circuit using third-order polynomial interpolation

Zero- and third-order digital-to-analog conversion techniques are described, and the theoretical error performances are compared. The design equations and procedures for constructing a third-order digital-to-analog converter by using analog design elements are presented. Both a zero- and a third-order digital-to-analog converter were built, and the performances are compared with various signal inputs.

Dotson, W. P., Jr.↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
NASA NTRS1970

Digital-voltage curve generator

Curve generator capable of producing precisely repeatable curve for any single-valued function of voltage versus time uses digital approach, implemented by means of clocked feedback shift register, large scale integrated circuit diode matrix comprising about 12,000 diodes, counter, and digital-to-analog converter.

Perlman, M.↗
NASA NTRS1974

Stereoscopic computer graphics display system

Handbook was published on study which describes relative merits of two general-purpose, steroscopic display systems. Both systems are adaptable to most small data processing facilities and, with minimal hardware development, greatly enhance user ability to interact with computer and to interpret data output. Section also describes digital-to-analog converters designed for use with system.

Plott, H. H., Jr.↗
NASA NTRS1974

A computer-controlled, on-board data acquisition system for wind-tunnel testing

A computer-controlled data acquisition system has been developed for the 40x80-foot wind tunnel at Ames Research Center. The system, consisting of several small onboard units installed in the model and a data-managing, data-displaying ground station, is capable of sampling up to 256 channels of raw data at a total sample rate of 128,000 samples/sec. Complete signal conditioning is contained within the on-board units. The sampling sequence and channel gain selection is completely random and under total control of the ground station. Outputs include a bar-graph display, digital-to-analog converters, and digital interface to the tunnel's central computer, an SEL 840MP. The system can be run stand-alone or under the control of the SEL 840MP.

Finger, H. J.↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗